<> <> <> <> <> <<>> DIRECTORY Core, CoreClasses, CoreCreate, ICTest, Rosemary, Ports, Rope, TestCable; EUTestChip: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, ICTest, Rosemary, Ports, TestCable = BEGIN OPEN CoreCreate; <<-- Prepares a test of the actual chip>> Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData, -- 32 bits KBus, -- 32 bits EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, -- 4 bits Dragon.ALUOps EUCondSel2AB, -- 4 bits Dragon.CondSelects EUCondition2B, DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT; euTest: Rope.ROPE = "EU2 Test"; allOnes: LONG CARDINAL _ LOOPHOLE[LONG[-1]]; Initialize: PROC [public: Wire] = { [Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData] _ Ports.PortIndexes[public, "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", "DPRejectB", "DPData"]; [KBus, EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, EUCondSel2AB, EUCondition2B] _ Ports.PortIndexes[public, "KBus", "EURdFromPBus3AB", "EUWriteToPBus3AB", "EUAluOp2AB", "EUCondSel2AB", "EUCondition2B"]; [DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd] _ Ports.PortIndexes[public, "DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", "DStAd"]; [] _ Rosemary.SetFixedWire[public[Vdd], H]; [] _ Rosemary.SetFixedWire[public[Gnd], L]; [] _ Rosemary.SetFixedWire[public[PadVdd], H]; [] _ Rosemary.SetFixedWire[public[PadGnd], L]; [] _ Ports.InitTesterDrive[public[PhA], force]; [] _ Ports.InitTesterDrive[public[PhB], force]; [] _ Ports.InitTesterDrive[public[DPRejectB], force]; [] _ Ports.InitPort[public[DPData], lc]; [] _ Ports.InitTesterDrive[public[DPData], expect]; [] _ Ports.InitPort[public[KBus], lc]; [] _ Ports.InitTesterDrive[public[KBus], force]; [] _ Ports.InitTesterDrive[public[EURdFromPBus3AB], force]; [] _ Ports.InitTesterDrive[public[EUWriteToPBus3AB], force]; [] _ Ports.InitPort[public[EUAluOp2AB], c]; [] _ Ports.InitTesterDrive[public[EUAluOp2AB], force]; [] _ Ports.InitPort[public[EUCondSel2AB], c]; [] _ Ports.InitTesterDrive[public[EUCondSel2AB], force]; [] _ Ports.InitTesterDrive[public[EUCondition2B], expect]; [] _ Ports.InitTesterDrive[public[DShA], force]; [] _ Ports.InitTesterDrive[public[DShB], force]; [] _ Ports.InitTesterDrive[public[DShRd], force]; [] _ Ports.InitTesterDrive[public[DShWt], force]; [] _ Ports.InitTesterDrive[public[DShIn], force]; [] _ Ports.InitTesterDrive[public[DShOut], expect]; [] _ Ports.InitTesterDrive[public[DHold], force]; [] _ Ports.InitPort[public[DStAd], c]; [] _ Ports.InitTesterDrive[public[DStAd], force]; }; <<>> <<-- a copy of a proc in EUUtils; make sure it is consistent!!!>> GenWiresForBonnie: PROC RETURNS [public: Wire] ~ { public _ WireList[LIST[ "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", Seq["DPData", 32], "DPRejectB", Seq["KBus", 32], "EURdFromPBus3AB", "EUWriteToPBus3AB", Seq["EUAluOp2AB", 4], Seq["EUCondSel2AB", 4], "EUCondition2B", "DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", Seq["DStAd", 4] ]]; }; TestChip: PROC [] ~ { R: PROC [a: ICTest.Assignments] = {assignments _ CONS[a, assignments]}; period: ICTest.Period; assignments: LIST OF ICTest.Assignments _ NIL; groups: LIST OF ICTest.Group _ NIL; ct: CellType _ CoreClasses.CreateUnspecified[ public: GenWiresForBonnie[], name: "EUForTester"]; Initialize[ct.public]; <<-- Real speed>> <> <> <<[number: 1, name: "DPData", directionality: biDirectional, format: DNRZ, delay: 5, sample: 40],>> <<[number: 2, name: "KBus", directionality: biDirectional, format: DNRZ, delay: 5, sample: 40],>> <<[number: 3, name: "Inputs", directionality: force, format: DNRZ, delay: 5],>> <<[number: 4, name: "Outputs", directionality: acquire, sample: 40],>> <<[number: 5, name: "Clocks", directionality: force, format: RZ, delay: 0, width: 45]>> <<];>> -- Half speed period _ 100; groups _ LIST[ [number: 1, name: "DPData", directionality: biDirectional, format: DNRZ, delay: 5, sample: 80], [number: 2, name: "KBus", directionality: biDirectional, format: DNRZ, delay: 5, sample: 80], [number: 3, name: "Inputs", directionality: force, format: DNRZ, delay: 5], [number: 4, name: "Outputs", directionality: acquire, sample: 80], [number: 5, name: "Clocks", directionality: force, format: RZ, delay: 0, width: 90] ]; <<-- Very slow test>> <> <> <<[number: 1, name: "DPData", directionality: biDirectional, format: DNRZ, delay: 10, sample: 200],>> <<[number: 2, name: "KBus", directionality: biDirectional, format: DNRZ, delay: 10, sample: 200],>> <<[number: 3, name: "Inputs", directionality: force, format: DNRZ, delay: 10],>> <<[number: 4, name: "Outputs", directionality: acquire, sample: 200],>> <<[number: 5, name: "Clocks", directionality: force, format: RZ, delay: 0, width: 500]>> <<];>> << L >> << o >> << a T >> << d e >> << s >> << B t D >> << o e U >> << a P r T >> << r o C D>> << d d h H H U>> << G B a e e T>> << r o S P B n a a >> << o a i a y n d d P>> << u r d i t e e e i>> <> R[["Vdd", 0, 0,R,AB, A,0,001,001, 1]]; R[["Gnd", 0, 0,R,AB, A,0,001,001, 1]]; R[["PadVdd", 0, 0,R,AB, A,0,001,001, 1]]; R[["PadGnd", 0, 0,R,AB, A,0,001,001, 1]]; R[["VRef", 0, 0,R,AB, A,0,001,107,232]]; R[["SensorA", 0, 0,R,AB, A,0,001,171,135]]; R[["SensorB", 0, 0,R,AB, A,0,001,170,136]]; R[["DPData[0]", 1, 1,R,CD, B,7, 40,190,151]]; --MSB R[["DPData[1]", 1, 1,R,CD, B,6, 39,189,152]]; R[["DPData[2]", 1, 1,R,CD, B,5, 38,186,155]]; R[["DPData[3]", 1, 1,R,CD, B,4, 37,184,157]]; R[["DPData[4]", 1, 1,R,CD, B,3, 36,181,160]]; R[["DPData[5]", 1, 1,R,CD, B,2, 35, 62,161]]; R[["DPData[6]", 1, 1,R,CD, B,1, 34, 34,164]]; R[["DPData[7]", 1, 1,R,CD, B,0, 33, 64,166]]; R[["DPData[8]", 1, 1,R,CD, A,7, 48,121,168]]; R[["DPData[9]", 1, 1,R,CD, A,6, 47,160,169]]; R[["DPData[10]", 1, 1,R,CD, A,5, 46,158,171]]; R[["DPData[11]", 1, 1,R,CD, A,4, 45,157,172]]; R[["DPData[12]", 1, 1,R,CD, A,3, 44,154,175]]; R[["DPData[13]", 1, 1,R,CD, A,2, 43,153,176]]; R[["DPData[14]", 1, 1,R,CD, A,1, 42,146,179]]; R[["DPData[15]", 1, 1,R,CD, A,0, 41, 40,181]]; R[["DPData[16]", 1, 0,R,AB, B,7, 24, 41,183]]; R[["DPData[17]", 1, 0,R,AB, B,6, 23, 43,185]]; R[["DPData[18]", 1, 0,R,AB, B,5, 22, 85,188]]; R[["DPData[19]", 1, 0,R,AB, B,4, 21, 84,189]]; R[["DPData[20]", 1, 0,R,AB, B,3, 20, 81,192]]; R[["DPData[21]", 1, 0,R,AB, B,2, 19, 90,193]]; R[["DPData[22]", 1, 0,R,AB, B,1, 18, 94,195]]; R[["DPData[23]", 1, 0,R,AB, B,0, 17, 93,196]]; R[["DPData[24]", 1, 0,R,AB, A,7, 32, 91,198]]; R[["DPData[25]", 1, 0,R,AB, A,6, 31,110,200]]; R[["DPData[26]", 1, 0,R,AB, A,5, 30, 19,203]]; R[["DPData[27]", 1, 0,R,AB, A,4, 29, 22,204]]; R[["DPData[28]", 1, 0,R,AB, A,3, 28, 46,207]]; R[["DPData[29]", 1, 0,R,AB, A,2, 27, 98,209]]; R[["DPData[30]", 1, 0,R,AB, A,1, 26,135,212]]; R[["DPData[31]", 1, 0,R,AB, A,0, 25,134,213]]; --LSB R[["KBus[0]", 2, 2,R,EF, A,0, 57,112, 90]]; --MSB R[["KBus[1]", 2, 2,R,EF, A,1, 58, 96, 89]]; R[["KBus[2]", 2, 2,R,EF, A,2, 59, 67, 86]]; R[["KBus[3]", 2, 2,R,EF, A,3, 60,115, 84]]; R[["KBus[4]", 2, 2,R,EF, A,4, 61,118, 81]]; R[["KBus[5]", 2, 2,R,EF, A,5, 62,248, 80]]; R[["KBus[6]", 2, 2,R,EF, A,6, 63,251, 77]]; R[["KBus[7]", 2, 2,R,EF, A,7, 64,253, 75]]; R[["KBus[8]", 2, 2,R,EF, B,0, 56,255, 73]]; R[["KBus[9]", 2, 2,R,EF, B,1, 55,256, 72]]; R[["KBus[10]", 2, 2,R,EF, B,2, 54,150, 70]]; R[["KBus[11]", 2, 2,R,EF, B,3, 53,151, 69]]; R[["KBus[12]", 2, 2,R,EF, B,4, 52, 70, 66]]; R[["KBus[13]", 2, 2,R,EF, B,5, 51, 71, 65]]; R[["KBus[14]", 2, 2,R,EF, B,6, 50, 73, 62]]; R[["KBus[15]", 2, 2,R,EF, B,7, 49,241, 60]]; R[["KBus[16]", 2, 3,R,GH, A,0,185,245, 57]]; R[["KBus[17]", 2, 3,R,GH, A,1,186,246, 56]]; R[["KBus[18]", 2, 3,R,GH, A,2,187,229, 53]]; R[["KBus[19]", 2, 3,R,GH, A,3,188,230, 52]]; R[["KBus[20]", 2, 3,R,GH, A,4,189,233, 49]]; R[["KBus[21]", 2, 3,R,GH, A,5,190,234, 48]]; R[["KBus[22]", 2, 3,R,GH, A,6,191,236, 46]]; R[["KBus[23]", 2, 3,R,GH, A,7,192,237, 45]]; R[["KBus[24]", 2, 3,R,GH, B,0,177,208, 43]]; R[["KBus[25]", 2, 3,R,GH, B,1,178,240, 41]]; R[["KBus[26]", 2, 3,R,GH, B,2,179,210, 38]]; R[["KBus[27]", 2, 3,R,GH, B,3,180,226, 37]]; R[["KBus[28]", 2, 3,R,GH, B,4,181,212, 34]]; R[["KBus[29]", 2, 3,R,GH, B,5,182,228, 32]]; R[["KBus[30]", 2, 3,R,GH, B,6,183,216, 29]]; R[["KBus[31]", 2, 3,R,GH, B,7,184,217, 28]]; --LSB R[["PhB", 5, 6,L,CD, A,1,170, 86,231]]; R[["PhA", 5, 6,L,CD, A,0,169, 88,229]]; R[["DShOut", 4, 6,L,AB, A,1,154,162,119]]; R[["EUCondition2B", 4, 6,L,AB, A,0,153,108,235]]; R[["DStAd[0]", 3, 5,R,KL, A,4,197,142,123]]; R[["DStAd[1]", 3, 5,R,KL, A,3,196,141,124]]; R[["DStAd[2]", 3, 5,R,KL, A,2,195,139,126]]; R[["DStAd[3]", 3, 5,R,KL, A,1,194,138,127]]; R[["DHold", 3, 5,R,KL, A,0,193,144,121]]; R[["DShIn", 3, 4,R,IJ, B,7,224, 26,116]]; R[["DShWt", 3, 4,R,IJ, B,6,223, 25,115]]; R[["DShRd", 3, 4,R,IJ, B,5,222, 61,112]]; R[["DShB", 3, 4,R,IJ, B,4,221, 74,111]]; R[["DShA", 3, 4,R,IJ, B,3,220, 76,109]]; R[["EUCondSel2AB[0]", 3, 4,R,IJ, B,2,219,199, 9]]; R[["EUCondSel2AB[1]", 3, 4,R,IJ, B,1,218,197, 12]]; R[["EUCondSel2AB[2]", 3, 4,R,IJ, B,0,217,196, 13]]; R[["EUCondSel2AB[3]", 3, 4,R,IJ, A,7,208,195, 15]]; R[["EUAluOp2AB[0]", 3, 4,R,IJ, A,6,207,101,240]]; R[["EUAluOp2AB[1]", 3, 4,R,IJ, A,5,206,205, 3]]; R[["EUAluOp2AB[2]", 3, 4,R,IJ, A,4,205,203, 5]]; R[["EUAluOp2AB[3]", 3, 4,R,IJ, A,3,204,200, 8]]; R[["EUWriteToPBus3AB", 3, 4,R,IJ, A,2,203,102,239]]; R[["EURdFromPBus3AB", 3, 4,R,IJ, A,1,202,105,236]]; R[["DPRejectB", 3, 4,R,IJ, A,0,201, 89,228]]; TestCable.Init[groups, assignments, "PhA", "PhB"]; ICTest.MakeStandardViewer[ testName: euTest, cellType: ct, clockAName: "PhA", clockBName: "PhB", groups: groups, assignments: assignments, period: period]; ICTest.RegisterTestProc[euTest, "TestCable", TestCable.TestCable]; }; END.