EUInner.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Louis Monier April 15, 1986 11:32:41 am PST
Last Edited by: Louis Monier October 28, 1986 6:20:08 pm PST
DIRECTORY Core, EUUtils;
EUInner: CEDAR DEFINITIONS =
BEGIN
CreateEUInner: PROC [] RETURNS [Core.CellType];
CreateControl: PROC [] RETURNS [Core.CellType];
CreateRamControl: PROC [] RETURNS [Core.CellType];
CreateSCControl: PROC [] RETURNS [Core.CellType];
CreateDPControl: PROC [] RETURNS [Core.CellType];
CreateDataPath: PROC [] RETURNS [Core.CellType];
CreateEURam:
PROC []
RETURNS [Core.CellType];
-- (ramA, ramB, cBus)[0..32), (selA, selB, selC)[0..40), (selALow, selBLow, selCLow)[0..4), Vdd, Gnd, nPrech
CreateRamTop:
PROC
RETURNS [cellType: Core.CellType];
-- (naBit, bBit, cBit, ncBit)[0..32)[0..4), nPrech, Vdd, Gnd
CreateRamArray:
PROC
RETURNS [cellType: Core.CellType];
-- (naBit, bBit, cBit, ncBit)[0..32)[0..4), (selA, selB, selC)[0..nRows), Vdd, Gnd
CreateRamMux:
PROC
RETURNS [cellType: Core.CellType];
-- (naBit, bBit, cBit, ncBit)[0..4)[0..32), (na, b, c, nc)[0..32), (selALow, selBLow, selCLow)[0..4), Gnd
CreateRamReadWrite:
PROC
RETURNS [cellType: Core.CellType];
-- (na, b, c, nc, ramA, ramB, cBus)[0..32), Vdd, Gnd
-- The order of bits here is the wrong Mesa order, i.e. the high-order bit is 0. However, the carry out was called c32, for the sake of confusion. It is renamed carryOut.
-- The "zero" bit out of the ALU is not what you think: it is p0.31 which is obtained at the top of the tree iff a-b=0, i.e. a+~b+1=0, i.e. a+~b=11111...111, i.e a=b. Thus, this bit is meaningful only after a VSub!
CreateALU: PROC [] RETURNS [Core.CellType];
Tree: PUBLIC PROC RETURNS [Core.Wire];
CreateFunctionBlock: PUBLIC PROC RETURNS [cellType: Core.CellType];
CreateCarryProp: PUBLIC PROC RETURNS [cellType: Core.CellType];
CreateFieldUnit:
PROC []
RETURNS [Core.CellType];
-- (left, st2A, r2B, cBus, fuOut)[0..32), insert, (mask, shift)[0..6), sh[0..33)
CreateBarrelShifter:
PROC
RETURNS [cellType: Core.CellType];
-- shOut[0..32), sh[0..33), pass, (left, st2A, r2B, cBus, fuOut)[0..32), Vdd, Gnd
CreateMask:
PROC
RETURNS [cellType: Core.CellType];
-- mask[0..6), shift[0..6), (m1, m2, st2A, r2B, cBus, fuOut)[0..32), Vdd, Gnd,
CreateCompose:
PROC
RETURNS [cellType: Core.CellType];
-- Vdd, Gnd, insert, (st2A, r2B, cBus, fuOut, shOut, m1, m2)[0..32)
CreateReg: PROC [reg: EUUtils.PipeRange] RETURNS [cellType: Core.CellType];
CreatePDriver: PROC RETURNS [cellType: Core.CellType];
CreateShRegDriver: PROC RETURNS [cellType: Core.CellType];
CreatekRegAndShift: PROC [] RETURNS [Core.CellType];
END.