EUImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Louis Monier June 17, 1986 8:06:14 pm PDT
McCreight, May 12, 1986 12:23:08 pm PDT
Bertrand Serlet August 11, 1986 11:58:20 pm PDT
Barth, April 19, 1986 5:25:00 pm PST
Last Edited by: Louis Monier January 26, 1987 11:29:56 pm PST
DIRECTORY CMosB, CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, Dragon, EU, EUArith, EUInner, EUUtils, PadFrame, Ports, PWCore, Rosemary;
EUImpl: CEDAR PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, EUArith, EUInner, EUUtils, PadFrame, Ports, PWCore, Rosemary
EXPORTS EU =
BEGIN OPEN EU, CoreCreate;
public: Wire ← EUUtils.GenWiresForBonnie[];
EUName: ROPE = Rosemary.Register[roseClassName: "EU", init: EUInit, evalSimple: EUSimple];
AssertionFailed: SIGNAL [message: ROPE] = CODE;
Assert: PROC [condition: BOOL, message: ROPE ← NIL] =
{IF NOT condition THEN SIGNAL AssertionFailed[message]};
MoreThanOne: PROC [a, b, c, d: BOOL ← FALSE] RETURNS [BOOL ← FALSE] ~ {
BtoN: PROC [b: BOOL] RETURNS [NAT] ~ {RETURN[IF b THEN 1 ELSE 0]};
RETURN[BtoN[a]+BtoN[b]+BtoN[c]+BtoN[d]>1];
};
CreateEU: PUBLIC PROC [ typeData: REF EUTypeData ← NIL, fullEU: BOOL ← FALSE, useCkPt: BOOL ← FALSE] RETURNS [ cellType: CellType ] = {
props: Properties ← CoreProperties.Props[[$ClusterInfo, typeData]];
SELECT TRUE FROM
~fullEU => cellType ← CoreClasses.CreateUnspecified[public, EUName, props];
fullEU AND ~useCkPt => {
cellType ← EUUtils.Fetch["EU"];
IF cellType=NIL THEN {
cellType ← CreateFullEU[props];
EUUtils.Store["EU", cellType];
}};
ENDCASE => cellType ← CoreIO.RestoreCellType[EUName];
CoreProperties.PutCellTypeProp[cellType, $ClusterInfo, typeData];
Ports.InitPorts[cellType, lc, none, "DPData", "KBus"];
Ports.InitPorts[cellType, c, none, "EUAluOp2AB", "EUCondSel2AB"];
Ports.InitPorts[cellType, b, drive, "EUCondition2B", "DShOut"];
[] ← Rosemary.BindCellType[cellType: cellType, roseClassName: EUName];
[] ← CoreFlat.CellTypeCutLabels[cellType, "EU"];
};
EUInit: Rosemary.InitProc = {
state: EUState ← NEW[EUStateRec -- [ nRegs ] -- ];
{OPEN state;
[Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData] ←
Ports.PortIndexes[cellType.public, "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", "DPRejectB", "DPData"];
[KBus, EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, EUCondSel2AB, EUCondition2B] ←
Ports.PortIndexes[cellType.public, "KBus", "EURdFromPBus3AB", "EUWriteToPBus3AB", "EUAluOp2AB", "EUCondSel2AB", "EUCondition2B"];
[DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd] ←
Ports.PortIndexes[cellType.public, "DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", "DStAd"];
data ← NARROW[CoreProperties.GetCellTypeProp[cellType, $ClusterInfo]];
FOR i: NAT IN [0..nRegs) DO ram[i] ← 0 ENDLOOP;
ram[EUUtils.constAdr+1] ← 1;
ram[EUUtils.constAdr+2] ← 2;
ram[EUUtils.constAdr+3] ← 3;
};
stateAny ← state;
};
-- shRegB[msb] goes out first
ShiftByOne: PROC [bIn: BOOL, shRegA, shRegB: CARD] RETURNS [newShRegA, newShRegB: CARD] ~ {
newShRegA ← shRegA;
newShRegB ← shRegB;
};
EUSimple: Rosemary.EvalProc = {
state: EUState ← NARROW[stateAny];
{OPEN state;
aAdr, bAdr, cAdr: CARD; -- actually, only bytes
lSrc, rSrc, stSrc: NAT;
st3IsC: BOOL;
p[KBus].d ← p[DPData].d ← none;
-- DBus stuff
IF p[DHold].b THEN { -- this chip is selected and frozen
Assert[NOT MoreThanOne[p[DShRd].b, p[DShWt].b, p[DShA].b, p[DShB].b], "DBus signals in illegal configuration"];
SELECT TRUE FROM
p[DShRd].b => {
regAd: NAT ← p[DStAd].c;
shRegA ← reg[regAd];};
p[DShWt].b => {
regAd: NAT ← p[DStAd].c;
reg[regAd] ← shRegB;};
p[DShA].b => [shRegA, shRegB] ← ShiftByOne[p[DShIn].b, shRegA, shRegB];
p[DShB].b => {
shRegB ← shRegA;
p[DShOut].b ← EUArith.EBFLC[shRegB, 0];};
ENDCASE => NULL;
RETURN};
-- PhA phase. Note that rejectBA alone inhibits almost any state change during PhA
IF p[PhA].b THEN {
cAdrInRAM: CARD;  -- different from cAdr in case of reject
-- This instruction must be the first one of PhA!
-- We select dataIn only in the case of a fetch without reject
cBusVal: CARD ← IF NOT rejectBA AND readPBusBA
THEN reg[dataIn]
ELSE reg[r3B];
-- Updating the RAM addresses and various control bits; notice the role of reject
[aAdr, bAdr, cAdr, st3IsC, lSrc, rSrc, stSrc] ← EUArith.ExplodeKReg[reg[kReg]];
-- On every PhA with RejectBA the faulty address is saved in ram[euMAR]; the EU generates the appropriate cAdrInRAM when RejectBA is sensed, so the rule is: we always write into the register file!
cAdrInRAM ← IF rejectBA THEN EUUtils.marAdr ELSE cAdr; -- force address on reject
IF cAdr=EUUtils.IFUAdr THEN {p[KBus].d ← drive; p[KBus].lc ← cBusVal};
IF cAdrInRAM IN [EUUtils.stackAdr .. EUUtils.bogusAdr) THEN ram[cAdrInRAM] ← cBusVal
ELSE Assert[FALSE, "EU cAdr out of range"];
-- I don't know who wrote this, so I treat it as a black box (LMM)
IF cAdr # EUUtils.junkAdr THEN {
IF data # NIL AND data.noteStore # NIL AND NOT data.storeNoted THEN {
data.noteStore[data: data.data, reg: cAdrInRAM, value: cBusVal];
data.storeNoted ← TRUE;
};
};
IF ~rejectBA AND ~conditionBA THEN carryAB ← carryBA;
IF ~rejectBA THEN {
IF cAdr=EUUtils.fieldAdr THEN reg[field] ← cBusVal;
reg[left] ← SELECT Dragon.ALULeftSources[VAL[lSrc]] FROM
aBus  => ram[aAdr],
rBus  => reg[r2B],
cBus  => cBusVal,
ENDCASE => ERROR;
reg[right] ← SELECT Dragon.ALURightSources[VAL[rSrc]] FROM
bBus  => ram[bAdr],
rBus  => reg[r2B],
cBus  => cBusVal,
kBus  => p[KBus].lc,
fCtlReg => reg[field],
ENDCASE => ERROR;
reg[st2A] ← SELECT Dragon.Store2ASources[VAL[stSrc]] FROM
bBus   => ram[bAdr],
cBus   => cBusVal,
rBus   => reg[r2B],
ENDCASE => ERROR;
reg[r3A] ← reg[r2B];
reg[st3A] ← IF st3IsC THEN cBusVal ELSE reg[st2B];
p[DPData].d ← drive; -- Send address to Cache only once: the cache latches it.
p[DPData].lc ← reg[r2B];
};
}
ELSE IF data # NIL THEN data.storeNoted ← FALSE;
-- PhiB phase. Most of the computations take place during PhB
IF p[PhB].b THEN {
aluOut, fuOut: CARD; -- temporary
overflow, c32, lz, ez, il: BOOL;
aluOps: Dragon.ALUOps ← VAL[p[EUAluOp2AB].c];
DPRejectB is valid at the end of PhiB but bogus on PhiA, so it must be latched on PhiB.
rejectBA ← p[DPRejectB].b;
readPBusBA ← p[EURdFromPBus3AB].b;
-- Receive RAM addresses and control bits on KBus from IFU
reg[kReg] ← p[KBus].lc;
-- PBus: notice that in case of reject during a store, we keep sending the data even though it is useless; this could be changed if needed.
Assert[NOT (p[EUWriteToPBus3AB].b AND p[EURdFromPBus3AB].b)];
reg[r3B] ← reg[r3A]; -- copy address
reg[dataIn] ← p[DPData].lc; -- latch whatever comes from the pads
-- Driving the PBus in case of a store
IF p[EUWriteToPBus3AB].b THEN {
p[DPData].d ← drive;
p[DPData].lc ← reg[st3A]
};
-- Data pipe
reg[st2B] ← reg[st2A];
-- ALU computation
[aluOut, c32, carryBA] ← EUArith.ALUOperation[aluOps, reg[left], reg[right], carryAB];
-- FU computation
fuOut ← IF aluOps=FOP THEN EUArith.FieldOp[reg[left], reg[st2A], reg[right]] ELSE 0;
-- Now pick up the result
reg[r2B] ← SELECT aluOps FROM
BndChk => reg[left],
FOP => fuOut,
ENDCASE => aluOut;
-- Condition and trap generation
overflow ← ((c32 # EUArith.EBFLC[aluOut, 0]) # (EUArith.EBFLC[reg[left], 0] # EUArith.EBFLC[reg[right], 0]));
lz ← (c32#(EUArith.EBFLC[reg[left], 0]#EUArith.EBFLC[reg[right], 0]));
ez ← aluOut=0;
il ← EUArith.LispTest[reg[left]] OR EUArith.LispTest[reg[right]] OR EUArith.LispTest[aluOut];
conditionBA ← SELECT Dragon.CondSelects[VAL[p[EUCondSel2AB].c]] FROM
False  => FALSE,
EZ   => ez,
LZ   => lz, -- VSub<0
LE   => ez OR lz, -- VSub<=0,
NE  => ~ez,
GE   => ~lz, -- VSub>=0
GZ   => ~(ez OR lz), -- VSub>0,
OvFl  => overflow,
BC   => ~c32,
IL   => il, -- the 3 high-order bits must be the same for both operands and result
NotBC  => c32,
NotIL  => ~il,
ModeFault  => TRUE,
ENDCASE => ERROR Rosemary.Stop["Invalid EUCondition2B Code"];
p[EUCondition2B].b ← conditionBA;
};
}};
globalPos: NAT ← 0; -- add the increment, then put the pad
SetFirst: PROC [pos: NAT] = {globalPos ← pos};
Next: PROC [] RETURNS [NAT] = {RETURN[Move[1]]};
Move: PROC [delta: NAT] RETURNS [NAT] = {
globalPos ← globalPos+delta;
RETURN[globalPos]};
CreateFullEU: PROC [props: Properties ← NIL] RETURNS [cellType: CellType] = {
vSize: NAT = 41;
hSize: NAT = 50;
left: NAT = 0;
bottom: NAT = left+vSize; -- 41
right: NAT = bottom+hSize; -- 91
top: NAT = right+vSize;  -- 132
iL: CellInstances ← LIST [
Instance[PWCore.RotateCellType[EUInner.CreateEUInner[], $Rot90],
["dStateAd", "dStateAd"], ["hold", "hold"], ["reject", "reject"] ]];
dpData: Wire ← FindWire[public, "DPData"];
aluOp: Wire ← FindWire[public, "EUAluOp2AB"];
condSel: Wire ← FindWire[public, "EUCondSel2AB"];
kBus: Wire ← FindWire[public, "KBus"];
dStAd: Wire ← FindWire[public, "DStAd"];
-- Left side
SetFirst[left+10];
iL ← PadFrame.AddPad[iL, "DShA", $In, Next[], ["toChip", "shiftA"]]; -- new: 11
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]];
iL ← PadFrame.AddPad[iL, "DShB", $In, Next[], ["toChip", "shiftB"]];
iL ← PadFrame.AddPad[iL, "DShRd", $In, Next[], ["toChip", "read"]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]];
iL ← PadFrame.AddPad[iL, "DShWt", $In, Next[], ["toChip", "write"]];
iL ← PadFrame.AddPad[iL, "DShIn", $In, Next[], ["toChip", "shIn"]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]];
iL ← PadFrame.AddPad[iL, "DShOut", $Out, Next[], ["fromChip", "shOut"]];
iL ← PadFrame.AddPad[iL, "DHold", $In, Next[], ["toChip", "hold"]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]];
iL ← PadFrame.AddPad[iL, dStAd[0], $In, Next[], ["toChip", "dStateAd[0]"]];
iL ← PadFrame.AddPad[iL, dStAd[1], $In, Next[], ["toChip", "dStateAd[1]"]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]];
iL ← PadFrame.AddPad[iL, dStAd[2], $In, Next[], ["toChip", "dStateAd[2]"]];
iL ← PadFrame.AddPad[iL, dStAd[3], $In, Next[], ["toChip", "dStateAd[3]"]];
iL ← PadFrame.AddPad[iL, NIL, $Copyright, Next[]];
iL ← PadFrame.AddPad[iL, NIL, $Logo, Next[]];
iL ← PadFrame.AddPad[iL, NIL, $Name, Next[]];
-- Bottom side: msb(0) on the left
SetFirst[bottom];  -- 41
FOR i: NAT IN [0..16) DO
index: NAT ← 2*i;
iL ← PadFrame.AddPad[iL, dpData[index], $IOTst, Move[2],  -- s on 43
["toChip", Index["fromPBus", index]],
["fromChip", Index["toPBus", index]],
["enWA", "enWrtPBusPhA"],
["enWB", "enWrtPBusPhB"]];
iL ← PadFrame.AddPad[iL, dpData[index+1], $IOTst, Next[],  -- s on 44
["toChip", Index["fromPBus", index+1]],
["fromChip", Index["toPBus", index+1]],
["enWA", "enWrtPBusPhA"],
["enWB", "enWrtPBusPhB"]];
ENDLOOP;
SetFirst[bottom];  -- 42
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]];   -- v on 42
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]];
-- Right side: msb(0) on the left
SetFirst[right+8];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]];  -- v on 100
iL ← PadFrame.AddPad[iL, "DPRejectB", $In, Next[], ["toChip", "dpRejectB"]];
iL ← PadFrame.AddPad[iL, "PhA", $Clk, Next[], ["Clock", "phA"], ["nClock", "nPhA"]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]];
iL ← PadFrame.AddPad[iL, "PhB", $Clk, Next[], ["Clock", "phB"], ["nClock", "nPhB"]];
iL ← PadFrame.AddPad[iL, NIL, $PadVdd, Next[]];  -- former VRef
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]];
iL ← PadFrame.AddPad[iL, "EUCondition2B", $Out, Next[], ["fromChip", "condition"]];
iL ← PadFrame.AddPad[iL, "EURdFromPBus3AB", $In, Next[], ["toChip", "readPBus3AB"]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]];
iL ← PadFrame.AddPad[iL, "EUWriteToPBus3AB", $In, Next[], ["toChip", "writePBus"]];
iL ← PadFrame.AddPad[iL, aluOp[0], $In, Next[], ["toChip", "aluOp[0]"]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]];
iL ← PadFrame.AddPad[iL, aluOp[1], $In, Next[], ["toChip", "aluOp[1]"]];
iL ← PadFrame.AddPad[iL, aluOp[2], $In, Next[], ["toChip", "aluOp[2]"]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]];
iL ← PadFrame.AddPad[iL, aluOp[3], $In, Next[], ["toChip", "aluOp[3]"]];
iL ← PadFrame.AddPad[iL, condSel[0], $In, Next[], ["toChip", "condSel[0]"]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]];
iL ← PadFrame.AddPad[iL, condSel[1], $In, Next[], ["toChip", "condSel[1]"]];
iL ← PadFrame.AddPad[iL, condSel[2], $In, Next[], ["toChip", "condSel[2]"]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]];
iL ← PadFrame.AddPad[iL, condSel[3], $In, Next[], ["toChip", "condSel[3]"]];
-- Top side
SetFirst[top]; -- 132
FOR i: NAT IN [0..16) DO
index: NAT ← 31-2*i;
iL ← PadFrame.AddPad[iL, kBus[index], $IOTst, Move[2],  -- s on 134
["toChip", Index["fromIFU", index]],
["fromChip", Index["toIFU", index]],
["enWA", "enWrtIFUPhA"],
["enWB", "enWrtIFUPhB"]];
iL ← PadFrame.AddPad[iL, kBus[index-1], $IOTst, Next[],  -- s on 135
["toChip", Index["fromIFU", index-1]],
["fromChip", Index["toIFU", index-1]],
["enWA", "enWrtIFUPhA"],
["enWB", "enWrtIFUPhB"]];
ENDLOOP;
SetFirst[top]; -- 132
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]];  -- v on 133
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]];
iL ← PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]];
cellType ← Cell[name: EUName,
public: public,
onlyInternal: EUUtils.GenWiresForOnion[],
instances: iL,
props: props];
PWCore.SetLayout[cellType, $PadFrame, PadFrame.padFrameParamsProp, NEW[PadFrame.PadFrameParametersRec ← [
nbPadsX: hSize,
nbPadsY: vSize,
horizLayer: "metal2",
vertLayer: "metal",
centerDisplacement: [-200*CMosB.lambda, 0]]]];
};
END.