<> <> <> <> <> DIRECTORY BitOps, CD, CoreCreate, EUInner, EUUtils, PWCore, Rope, TilingClass; EUFUImpl: CEDAR PROGRAM IMPORTS BitOps, CoreCreate, EUUtils, PWCore, Rope, TilingClass EXPORTS EUInner = BEGIN OPEN CoreCreate, EUInner; <<-- (left, st2A, r2B, cBus, fuOut)[0..32), insert, (mask, shift)[0..6), sh[0..33)>> CreateFieldUnit: PUBLIC PROC RETURNS [cellType: CellType] = { cellType _ EUUtils.Extract["FieldUnit.sch"]; }; <<>> <<-- A barrel shifter; two inputs (left and st2A), one output (fuOut)>> <<-- sh=0 => out_left; sh=32 => out_st2A; shift by zero is on top;>> <<-- shOut[0..32), sh[0..33), pass, (left, st2A, r2B, cBus, fuOut)[0..32), Vdd, Gnd>> CreateBarrelShifter: PUBLIC PROC RETURNS [cellType: CellType] = { sh: Wire _ Seq["sh", 32+1]; shOut: Wire _ Seq["shOut", 32]; left: Wire _ Seq["left", 32]; st2A: Wire _ Seq["st2A", 32]; r2B: Wire _ Seq["r2B", 32]; cBus: Wire _ Seq["cBus", 32]; fuOut: Wire _ Seq["fuOut", 32]; tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[35]]; <<-- 0 is the bottom>> tileArray[0] _ NEW[TilingClass.TileRowRec[32]]; FOR i: NAT IN [0..32) DO tileArray[0][i] _ NEW[TilingClass.TileRec _ [ type: EUUtils.Extract["shRightConnect.sch"], flatten: TRUE, renaming: LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"], ["st2A", st2A[i]], ["r2B", r2B[i]], ["cBus", cBus[i]], ["fuOut", fuOut[i]], ["shOut", shOut[i]] ] ]]; ENDLOOP; <<-- line n of shifter is tileArray[n+1]>> FOR row: NAT IN [1..33] DO tileArray[row] _ NEW[TilingClass.TileRowRec[32]]; FOR i: NAT IN [0..32) DO tileArray[row][i] _ NEW[TilingClass.TileRec _ [ type: EUUtils.Extract["ShifterCell.sch"], flatten: TRUE, renaming: LIST[["sh", sh[33-row]]] ]]; ENDLOOP; ENDLOOP; <<-- 34 is the top>> tileArray[34] _ NEW[TilingClass.TileRowRec[32]]; FOR i: NAT IN [0..32) DO tileArray[34][i] _ NEW[TilingClass.TileRec _ [ type: EUUtils.Extract["shLeftConnect.sch"], flatten: TRUE, renaming: LIST[ ["left", left[i]] ] ]]; ENDLOOP; cellType _ TilingClass.CreateTiling[ name: "BarrelShifter", public: Wires[shOut, sh, "Vdd", "Gnd", left, st2A, r2B, cBus, fuOut], tileArray: tileArray, neighborX: TilingClass.LayoutNeighborX, neighborY: TilingClass.LayoutNeighborY ]; }; <<>> <<-- The field unit uses a mask generator which takes two 6-bit quantities ("shift" and "mask") and a boolean (insert), and produces a mask of the form:>> <> <> <> <<-- A bit of mask generation theory: let k and i be two n+1-bit numbers, and F[n, k, i]=k>i. By recurring on the high-order bit, we find that >> <> <> <> << F[n, k, i]=k[n] + F[n-1, k, i]=Nand [~k[n], ~F[n-1, k, i]] (NOR to Gnd)>> <> << F[n, k, i]=k[n] . F[n-1, k, i]=Nor [~k[n], ~F[n-1, k, i]] (NAND branch)>> <<-- Note: a NAND branch starting with no tr. still has no tr., i.e. if i=xx0111 then the three bottom transistors are missing! >> <<>> <<-- mask[0..6), shift[0..6), (m1, m2, st2A, r2B, cBus, fuOut)[0..32), Vdd, Gnd, >> CreateMask: PUBLIC PROC RETURNS [cellType: CellType] = { instances: CellInstances _ NIL; FOR i: [0..32) DECREASING IN [0..32) DO instances _ CONS[ Instance[CreateMasksCell[i], ["m1", Index["m1", i]], ["m2", Index["m2", i]], ["st2A", Index["st2A", i]], ["r2B", Index["r2B", i]], ["cBus", Index["cBus", i]], ["fuOut", Index["fuOut", i]]], instances]; ENDLOOP; cellType _ Cell[ name: "Mask", public: Wires["Vdd", "Gnd", Seq["mask", 6], Seq["shift", 6], Seq["m1", 32], Seq["m2", 32], Seq["st2A", 32], Seq["r2B", 32], Seq["cBus", 32], Seq["fuOut", 32]], instances: instances]; PWCore.SetAbutX[cellType]; }; <<-- "Vdd", "Gnd", "shift[0..6)", "mask[0..6)", "m1", "m2", "st2A", "r2B", "cBus", "fuOut">> CreateMasksCell: PROC [pos: [0..32)] RETURNS [cellType: CellType] = { m1: CellType _ CreateMaskCell["mask", "m1", 31-pos]; m2: CellType _ CreateMaskCell["shift", "m2", 31-pos]; cellType _ Cell[ name: "Masks", public: Wires["Vdd", "Gnd", Seq["mask", 6], Seq["shift", 6], "m1", "m2", "st2A", "r2B", "cBus", "fuOut" ], instances: LIST[Instance[m2], Instance[m1]]]; PWCore.SetAbutY[cellType]; }; Trits: TYPE = {P, S, F, X}; Pat: TYPE = ARRAY [0..6) OF Trits; Pattern: PROC [k: NAT] RETURNS [lowToHi: Pat] ~ { <> isOne: BOOL _ BitOps.EBFD[k, 31]; -- low-order bit I believe lowToHi[0] _ IF isOne THEN X ELSE F; FOR bit: NAT IN [1..6) DO <> isOne _ BitOps.EBFD[k, 31-bit]; lowToHi[bit] _ SELECT TRUE FROM isOne AND lowToHi[bit-1]=X => X, isOne => S, ~isOne AND lowToHi[bit-1]=X => F, ~isOne => P, ENDCASE => ERROR; ENDLOOP; }; <<-- Using a generator of static gates, program maskOut=F(a, pos)>> <<-- "Vdd", "Gnd", "selName[0..6)", "maskOut">> <<-- (selName, outName) can be (mask, m1) or (shift, m2); >> CreateMaskCell: PROC [selName, outName: ROPE, pos: [0..32)] RETURNS [cellType: CellType] = { pas: LIST OF CoreCreate.PA _ LIST[["Vdd", "Vdd"], ["m1", "m1"], ["m2", "m2"], ["Gnd", "Gnd"], ["st2A", "st2A"], ["r2B", "r2B"], ["cBus", "cBus"], ["fuOut", "fuOut"]]; POb: CD.Object _ PWCore.Layout[EUUtils.Extract["maskP.sch"]]; SOb: CD.Object _ PWCore.Layout[EUUtils.Extract["maskS.sch"]]; FOb: CD.Object _ PWCore.Layout[EUUtils.Extract["maskF.sch"]]; XOb: CD.Object _ PWCore.Layout[EUUtils.Extract["maskX.sch"]]; botOb: CD.Object _ PWCore.Layout[EUUtils.Extract["maskBot.sch"]]; public: Wire _ Wires["Vdd", "Gnd", Seq[selName, 6], "m1", "m2", "st2A", "r2B", "cBus", "fuOut"]; abutInstances: LIST OF PWCore.AbutInstance _ LIST [ [PWCore.Layout[EUUtils.Extract[Rope.Cat[outName, "top.sch"]]], pas]]; lowToHi: Pat _ Pattern[pos]; FOR bit: NAT DECREASING IN [0..6) DO ob: CD.Object _ SELECT lowToHi[bit] FROM X => XOb, F => FOb, S => SOb, P => POb, ENDCASE => ERROR; abutInstances _ CONS [[ob, CONS[["sel", Index[selName, 5-bit]], pas]], -- check!!! abutInstances]; ENDLOOP; abutInstances _ CONS [[botOb, pas], abutInstances]; cellType _ PWCore.AbutCell[ name: "Mask", public: public, abutInstances: abutInstances, inX: FALSE]; }; <<>> <<-- The composition cell: two masks, two words, insert, and an output>> <<-- Vdd, Gnd, insert, (st2A, r2B, cBus, fuOut, shOut, m1, m2)[0..32)>> CreateCompose: PUBLIC PROC RETURNS [cellType: CellType] = { cellType _ EUUtils.CSeqX["Compose", EUUtils.Extract["ComposeCell.sch"], 32, LIST["st2A", "r2B", "cBus", "m1", "m2", "shOut", "fuOut"]]; }; <<>> END. <<>>