[Indigo]<Dragon>EU2Sim>EU2Utils.mesa!1

EU2Utils.mesa

Louis Monier April 1, 1986 3:56:16 pm PST

McCreight, March 31, 1986 3:34:56 pm PST

DIRECTORY CoreCreate, Dragon, Ports;

EU2Utils: CEDAR DEFINITIONS = BEGIN

OPEN CoreCreate;

-- The RAM

wordSize: NAT = 32;

nRows: NAT = 2; -- 40; one row is a Quadword

sizeSelLow: NAT = 4;

nbWords: NAT = sizeSelLow*nRows;

sizeAdrH: NAT = 6; -- for y-decoder

sizeAdrL: NAT = 2; -- for x-decoder

sizeRamAdr: NAT = 3*(sizeAdrH+sizeAdrL); -- 3 bytes

posH: ARRAY [a..c] OF NAT = [0, 8, 16];

posL: ARRAY [a..c] OF NAT = [6, 14, 22];

stackAdr, junkAdr, fieldAdr, marAdr, constAdr, IFUAdr, bogusAdr: NAT;

KernalLimit: LONG CARDINAL;

BndChk: NAT=3; FOP: NAT=10; -- from Dragon.mesa

-- Control signals from the IFU

sizeLeftSrc: NAT = 2;

sizeRightSrc: NAT = 3;

sizeSt2ASrc: NAT = 2;

sizeALUOps: NAT = 4;

sizeCondSelects: NAT = 4;

-- ALU

Carry: TYPE = {zero, one, comp, ncomp, prev, nprev};

ALUOpcode: TYPE = {add, and, or, xor};

ALUOpRec: TYPE = RECORD[

op: ALUOpcode,

invertB: BOOL ← FALSE,

cIn, cOut: Carry ← prev

];

aluOps: ARRAY Dragon.ALUOps OF ALUOpRec;

-- Field descriptor

sizeK: NAT = 6;

-- Bus sources and states

maxSel: NAT = 5;

maxBuses: NAT = 6;

Clock: TYPE = {phA, phB, none};

InputSels: TYPE = ARRAY [0..maxSel) OF SourceRange;

Buses: TYPE = LIST OF SourceRange;

PipeRange: TYPE = [left..cBus]; -- states

SourceRange: TYPE = [left..pIn];

Source: TYPE = RECORD[

name: ROPE ← NIL,

nameSel: ROPE ← NIL,

sizeSel: NAT ← 0,

tristate: BOOL ← FALSE,

trackPosX: [0..maxBuses) ← 0,

topOnlyBuses: Buses,

botOnlyBuses: Buses,

throughBuses: Buses, -- Vdd and Gnd are implicit

inputs: InputSels ← [0, 0, 0, 0, 0]

];

sources: READONLY ARRAY SourceRange OF Source;

-- pipeline registers

left: NAT = 0;

right: NAT = 1;

st2A: NAT = 2;

st2B: NAT = 3;

st3A: NAT = 4;

kReg: NAT = 5;

field: NAT = 6;

r2B: NAT = 7; -- rBus

r3A: NAT = 8; -- cBus

r3B: NAT = 9;

dataIn: NAT = 10;

cBus: NAT = 11;

-- other sources for buses, not states

pDriver: NAT = 12;

ramA: NAT = 13;

ramB: NAT = 14;

ifuIn: NAT = 15; -- kBus

semiCt: NAT = 16;

aluOut: NAT = 17;

fuOut: NAT = 18;

pIn: NAT = 19;

-- the bus used for debugging

dReadBus: ROPE;

-- Various indexings

hi, Hi: NAT = 0;

low, Low: NAT = 0;

a: NAT = 0;

b: NAT = 1;

c: NAT = 2;

PortIndex: PUBLIC PROC [wire: Wire, name: ROPE] RETURNS [NAT];

InitLeafPorts: PUBLIC PROC [public: Wire, initDrive: Ports.Drive];

Bus: PUBLIC PROC [name: ROPE ← NIL] RETURNS [Wire]; -- 32 wires

MySeq: PUBLIC PROC [name: ROPE, size: NAT, wire: Wire ← NIL] RETURNS [seqWire: Wire];

Name: PUBLIC PROC [name: ROPE, wire: Wire] RETURNS [Wire];

NameList: PUBLIC PROC [name: ROPE, wrs: LIST OF WR] RETURNS [wire: Wire];

AllBuses: PROC [reg: PipeRange] RETURNS [buses: Wire];

GenWiresForBonnie: PROC RETURNS [Wire];

GenPGnEWires: PROC RETURNS [Wire];

GenClockWires: PROC RETURNS [Wire];

GenWiresCtrlToPads: PROC RETURNS [Wire];

GenWiresPadsToCtrl: PROC RETURNS [Wire];

GenWiresDBus: PROC RETURNS [Wire];

GenWiresDPToPads: PROC RETURNS [Wire];

GenWiresForOnion: PROC RETURNS [Wire];

GenWiresCtrlToRam: PROC RETURNS [Wire];

GenWiresRamToCtrl: PROC RETURNS [Wire];

GenRegSelWire: PROC [reg: PipeRange] RETURNS [Wire];

GenWiresCtrlToRegs: PROC RETURNS [Wire];

GenWiresCtrlToALU: PROC RETURNS [Wire];

GenWiresCtrlToFU: PROC RETURNS [Wire];

GenWiresALUToCtrl: PROC RETURNS [Wire];

GenWiresDPToCtrl: PROC RETURNS [Wire];

GenWiresForRouter: PROC RETURNS [Wire];

END.