[Indigo]<Dragon>EU2Sim>EU2Impl.mesa!4

EU2Impl.mesa

Louis Monier April 2, 1986 9:08:38 am PST

McCreight, April 10, 1986 12:13:32 pm PST

Bertrand Serlet March 31, 1986 3:49:13 pm PST

DIRECTORY Core, CoreCreate, CoreProperties, Dragon, DragonRosemary, EU2, EU2Arith, EU2Utils, Ports, Rosemary;

EU2Impl: CEDAR PROGRAM

IMPORTS CoreCreate, CoreProperties, DragonRosemary, EU2Arith, EU2Utils, Ports, Rosemary

EXPORTS EU2 =

BEGIN OPEN EU2, EU2Arith, EU2Utils, CoreCreate;

public: Wire ← GenWiresForBonnie[];

Vdd: PUBLIC NAT ← PortIndex[public, "Vdd"];

Gnd: PUBLIC NAT ← PortIndex[public, "Gnd"];

PadVdd: PUBLIC NAT ← PortIndex[public, "PadVdd"];

PadGnd: PUBLIC NAT ← PortIndex[public, "PadGnd"];

PhA: PUBLIC NAT ← PortIndex[public, "PhA"];

PhB: PUBLIC NAT ← PortIndex[public, "PhB"];

DPData: PUBLIC NAT ← PortIndex[public, "DPData"];

DPRejectB: PUBLIC NAT ← PortIndex[public, "DPRejectB"];

KBus: PUBLIC NAT ← PortIndex[public, "KBus"];

EURes3BisPBus3AB: PUBLIC NAT ← PortIndex[public, "EURes3BisPBus3AB"];

EUWriteToPBus3AB: PUBLIC NAT ← PortIndex[public, "EUWriteToPBus3AB"];

EUAluOp2AB: PUBLIC NAT ← PortIndex[public, "EUAluOp2AB"];

EUCondSel2AB: PUBLIC NAT ← PortIndex[public, "EUCondSel2AB"];

EUCondition2B: PUBLIC NAT ← PortIndex[public, "EUCondition2B"];

DShiftAB: PUBLIC NAT ← PortIndex[public, "DShiftAB"];

DExecuteAB: PUBLIC NAT ← PortIndex[public, "DExecuteAB"];

DNSelectAB: PUBLIC NAT ← PortIndex[public, "DNSelectAB"];

DHoldAB: PUBLIC NAT ← PortIndex[public, "DHoldAB"];

DDataInAB: PUBLIC NAT ← PortIndex[public, "DDataInAB"];

DDataOutAB: PUBLIC NAT ← PortIndex[public, "DDataOutAB"];

CreateEU2: PUBLIC PROC [ typeData: REF EUTypeData ← NIL ] RETURNS [ cellType: CellType ] = {

cellType ← Cell[

name: "EU2",

public: public,

onlyInternal: GenWiresForOnion[],

instances: NIL,

props: CoreProperties.Props[[$ClusterInfo, typeData]]

];

[] ← Rosemary.SetFixedWire[cellType.public[Vdd], H];

[] ← Rosemary.SetFixedWire[cellType.public[Gnd], L];

[] ← Rosemary.SetFixedWire[cellType.public[PadVdd], H];

[] ← Rosemary.SetFixedWire[cellType.public[PadGnd], L];

[] ← Ports.InitPort[cellType.public[DPData], lc, none];

[] ← Ports.InitPort[cellType.public[KBus], lc, none];

[] ← Ports.InitPort[cellType.public[EUAluOp2AB], c, none];

[] ← Ports.InitPort[cellType.public[EUCondition2B], b, drive];

[] ← Ports.InitPort[cellType.public[EUCondSel2AB], c, none];

[] ← Rosemary.BindCellType[cellType: cellType, roseClassName: EU2RoseClass];

};

EU2RoseClass: ROPE = Rosemary.Register[roseClassName: "EU2", init: EU2Init, evalSimple: EU2Simple];

EU2Init: Rosemary.InitProc = {

state: EU2State ← NEW[EU2StateRec -- [ nRegs ] -- ];

state.data ← NARROW[CoreProperties.GetCellTypeProp[cellType, $ClusterInfo]];

FOR i: NAT IN [0..nRegs) DO

state.ram[i] ← 0;

ENDLOOP;

stateAny ← state;

};

EU2Simple: Rosemary.EvalProc = {

state: EU2State ← NARROW[stateAny];

{OPEN state;

aAdr, bAdr, cAdr: CARD; -- actually, only bytes

lSrc, rSrc, stSrc: NAT;

st3IsC: BOOL;

EUAluLeftSrc1BA: Dragon.ALULeftSources;

2 bits {aBus(0), rBus(1), cBus(2), reserve3(3)}

EUAluRightSrc1BA: Dragon.ALURightSources;

3 bits {bBus(0), rBus(1), cBus(2), kBus(3), fCtlReg(4)}

EUStore2ASrc1BA: Dragon.Store2ASources;

2 bits {bBus(0), rBus(1), cBus(2), reserve3(3)}

p[DPData].d ← none;

p[KBus].d ← none;

-- PhA phase. Note that rejectBA alone inhibits almost any state change during PhA

IF p[PhA].b THEN {

-- Better be first! We use the latched version of reject here, so no race.

simRegs[cBus] ← IF rejectBA THEN simRegs[r3B] ELSE simRegs[dataIn];

-- Updating the RAM addresses and various control bits; notice the role of reject

[aAdr, bAdr, cAdr, st3IsC, lSrc, rSrc, stSrc] ← EU2Arith.ExplodeKReg[simRegs[kReg]];

EUStore2ASrc1BA ← VAL[stSrc];

EUAluRightSrc1BA ← VAL[rSrc];

EUAluLeftSrc1BA ← VAL[lSrc];

IF rejectBA THEN cAdr ← marAdr; -- force address

-- On every PhA with RejectBA the faulty address is saved in ram[euMAR]; the EU generates the appropriate cAdr when RejectBA is sensed, so the rule is: we always write into the register file!

IF cAdr # junkAdr THEN {

IF data # NIL AND data.noteStore # NIL AND NOT data.storeNoted THEN {

data.noteStore[data: data.data, reg: cAdr, value: simRegs[cBus]];

data.storeNoted ← TRUE;

};

SELECT cAdr FROM

IFUAdr => {p[KBus].d ← drive; p[KBus].lc ← simRegs[cBus]};

IN [stackAdr .. bogusAdr) => ram[cAdr] ← simRegs[cBus];

ENDCASE => DragonRosemary.Assert[FALSE, "EU cAdr out of range"];

IF cAdr=fieldAdr THEN simRegs[field] ← simRegs[cBus];

};

IF ~rejectBA AND ~conditionBA THEN carryAB ← carryBA;

IF ~rejectBA THEN {

simRegs[left] ← SELECT EUAluLeftSrc1BA FROM

aBus => ram[aAdr],

rBus => simRegs[r2B],

cBus => simRegs[cBus],

ENDCASE => ERROR;

simRegs[right] ← SELECT EUAluRightSrc1BA FROM

bBus => ram[bAdr],

rBus => simRegs[r2B],

cBus => simRegs[cBus],

kBus => p[KBus].lc,

fCtlReg => simRegs[field],

ENDCASE => ERROR;

simRegs[st2A] ← SELECT EUStore2ASrc1BA FROM

bBus => ram[bAdr],

cBus => simRegs[cBus],

rBus => simRegs[r2B],

ENDCASE => ERROR;

simRegs[r3A] ← simRegs[r2B];

simRegs[st3A] ← IF st3IsC THEN simRegs[cBus] ELSE simRegs[st2B];

p[DPData].d ← drive; -- Send address to Cache only once: the cache latches it.

p[DPData].lc ← simRegs[r2B];

};

}

ELSE IF data # NIL THEN data.storeNoted ← FALSE;

-- PhiB phase. Most of the computations take place during PhB

IF p[PhB].b THEN {

aluOut, fuOut: CARD; -- temporary

overflow, c32, lz, ez, il: BOOL;

aluOps: Dragon.ALUOps ← VAL[p[EUAluOp2AB].c];

DPRejectB is valid at the end of PhiB but bogus on PhiA, so it must be latched by PhiB.

rejectBA ← p[DPRejectB].b;

-- Receive RAM addresses and control bits on KBus form IFU

simRegs[kReg] ← p[KBus].lc;

-- PBus: notice that in case of reject during a store, we keep sending the data even though it is useless

DragonRosemary.Assert[NOT (p[EUWriteToPBus3AB].b AND p[EURes3BisPBus3AB].b)];

simRegs[r3B] ← simRegs[r3A]; -- copy address

simRegs[dataIn] ← p[DPData].lc; -- latch whatever comes form the pads

-- In case of a fetch, an op, or a move, we are done

IF p[EUWriteToPBus3AB].b THEN { -- store in progress: sending data

p[DPData].d ← drive;

p[DPData].lc ← simRegs[st3A] -- send data to Cache (Store)

};

-- Data pipe

simRegs[st2B] ← simRegs[st2A];

-- ALU computation

[aluOut, c32, carryBA] ← EU2Arith.ALUOperation[aluOps, simRegs[left], simRegs[right], carryAB];

-- FU computation

fuOut ← IF aluOps=FOP THEN FieldOp[simRegs[left], simRegs[st2A], simRegs[right]] ELSE 0;

-- Now pick up the result

simRegs[r2B] ← SELECT aluOps FROM

BndChk => simRegs[left],

FOP => fuOut,

ENDCASE => aluOut;

-- Condition and trap generation

overflow ← ((c32 # EBFLC[aluOut, 0]) # (EBFLC[simRegs[left], 0] # EBFLC[simRegs[right], 0]));

lz ← (c32#(EBFLC[simRegs[left], 0]#EBFLC[simRegs[right], 0]));

ez ← aluOut=0;

il ← LispTest[simRegs[left]] OR LispTest[simRegs[right]] OR LispTest[aluOut];

conditionBA ← SELECT Dragon.CondSelects[VAL[p[EUCondSel2AB].c]] FROM

False => FALSE,

EZ => ez,

LZ => lz, -- VSub<0

LE => ez OR lz, -- VSub<=0,

AddressCheckFault => aluOut < KernalLimit,

NE => ~ez,

GE => ~lz, -- VSub>=0

GZ => ~(ez OR lz), -- VSub>0,

OvFl => overflow,

BC => ~c32,

IL => il, -- the 3 high-order bits must be the same for both operands and result

NotBC => c32,

NotIL => ~il,

ModeFault => TRUE,

ENDCASE => ERROR Rosemary.Stop["Invalid EUCondition2B Code"];

p[EUCondition2B].b ← conditionBA;

};

}};

END.