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0 0 WBB 0 0 WBC 0 0 WBD 0 0 WBE 0 0 WBF 0 0 WC0 0 0 WC1 0 0 WC2 0 0 WC3 0 0 WC4 0 0 WC5 0 0 WC6 0 0 WC7 0 0 WC8 0 0 WC9 0 0 WCA 0 0 WCB 0 1 A0 r R1 WCC 0 1 A0 r R0 2 A0 r R15 "shRegDriver" A1 a A3 AbutX RF 32 WCD 44 0 W1 W22 W23 W44 W45 W66 W87 W88 WA9 WAA WCB WCC WCE 12 0 W2 W22 W24 W44 W46 W67 W87 W89 WA9 WAB WCB WCC WCF 12 0 W3 W22 W25 W44 W47 W68 W87 W8A WA9 WAC WCB WCC WD0 12 0 W4 W22 W26 W44 W48 W69 W87 W8B WA9 WAD WCB WCC WD1 12 0 W5 W22 W27 W44 W49 W6A W87 W8C WA9 WAE WCB WCC WD2 12 0 W6 W22 W28 W44 W4A W6B W87 W8D WA9 WAF WCB WCC WD3 12 0 W7 W22 W29 W44 W4B W6C W87 W8E WA9 WB0 WCB WCC WD4 12 0 W8 W22 W2A W44 W4C W6D W87 W8F WA9 WB1 WCB WCC WD5 12 0 W9 W22 W2B W44 W4D W6E W87 W90 WA9 WB2 WCB WCC WD6 12 0 WA W22 W2C W44 W4E W6F W87 W91 WA9 WB3 WCB WCC WD7 12 0 WB W22 W2D W44 W4F W70 W87 W92 WA9 WB4 WCB WCC WD8 12 0 WC W22 W2E W44 W50 W71 W87 W93 WA9 WB5 WCB WCC WD9 12 0 WD W22 W2F W44 W51 W72 W87 W94 WA9 WB6 WCB WCC WDA 12 0 WE W22 W30 W44 W52 W73 W87 W95 WA9 WB7 WCB WCC WDB 12 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WA7 WA9 WC9 WCB WCC WED 12 0 W21 W22 W43 W44 W65 W86 W87 WA8 WA9 WCA WCB WCC WCE 1 A0 r R16 "shReg0" C2 W0 12 0 W1 0 2 A4 LichenStructureFromCoreImplWireColor i 37044 A0 r R13 W2 0 2 A4 i 65309 A0 r R9 W3 0 2 A4 i 25294 A0 r R4 W4 0 2 A4 i 290 A0 r RB W5 0 2 A4 i 51275 A0 r R14 W6 0 2 A4 i 53781 A0 r R5 W7 0 2 A4 i 30524 A0 r RA W8 0 2 A4 i 36582 A0 r R2 W9 0 2 A4 i 65307 A0 r R8 WA 0 2 A4 i 36584 A0 r R3 WB 0 2 A0 r R1 A4 i 53399 WC 0 2 A0 r R0 A4 i 3184 2 A0 r R17 "shReg" A1 a A5 Get RF 10 WD 16 0 W4 W8 W1 WE 0 0 W3 W5 W7 WA W6 WF 0 0 W10 0 0 W9 W11 0 0 W2 WC WB W12 3 0 W7 W11 W3 0 C3 W0 3 0 W1 0 2 A0 r R18 "gate" A4 i 47 W2 0 2 A0 r R19 "ch1" A4 i 834 W3 0 2 A0 r R1A "ch2" A4 i 834 1 A0 r R1B "nE(2/4)" R1C "Transistor" nE 2 4 W13 3 0 W9 W11 W5 0 C3 W14 4 0 WC WB W11 WF 0 C4 W0 4 0 W1 0 2 A0 r R0 A6 PortData l n W2 0 2 A0 r R1 A6 l n W3 0 2 A0 r R1D "Input" A6 l n W4 0 2 A0 r R1E "nOutput" A6 l d 3 A0 r R1F "Inverter" A7 RoseBehave r R1F A8 RoseCutSet lor 1 R20 "JustAboveTransistors" RF 2 W0 W5 3 0 W3 W1 W4 0 C5 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 RoseTransistorSize d A0 r R21 "pE(2/10)" R1C pE 2 10 W6 3 0 W3 W4 W2 0 C6 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 d A0 r R1B R1C nE 2 4 W15 4 0 WC WB WF W11 0 C7 W0 4 0 W1 0 2 A0 r R0 A6 l n W2 0 2 A0 r R1 A6 l n W3 0 2 A0 r R1D A6 l n W4 0 2 A0 r R1E A6 l dw 3 A0 r R1F A7 r R1F A8 lor 1 R20 RF 2 W0 W5 3 0 W3 W1 W4 0 C8 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 dw A0 r R21 R1C pE 2 10 W6 3 0 W3 W4 W2 0 C9 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 dw A0 r R1B R1C nE 2 4 W16 3 0 W2 W10 WF 0 C3 W17 4 0 WC WB W10 W1 0 C4 W18 4 0 WC WB W1 W10 0 C7 W19 4 0 WC WB W4 WE 0 C4 W1A 3 0 W4 W1 W3 0 C3 W1B 3 0 WE W1 W3 0 CA W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 1 A0 r R22 "pE(2/4)" R1C pE 2 4 WCF 1 A0 r R23 "shReg1" C2 WD0 1 A0 r R24 "shReg2" C2 WD1 1 A0 r R25 "shReg3" C2 WD2 1 A0 r R26 "shReg4" C2 WD3 1 A0 r R27 "shReg5" C2 WD4 1 A0 r R28 "shReg6" C2 WD5 1 A0 r R29 "shReg7" C2 WD6 1 A0 r R2A "shReg8" C2 WD7 1 A0 r R2B "shReg9" C2 WD8 1 A0 r R2C "shReg10" C2 WD9 1 A0 r R2D "shReg11" C2 WDA 1 A0 r R2E "shReg12" C2 WDB 1 A0 r R2F "shReg13" C2 WDC 1 A0 r R30 "shReg14" C2 WDD 1 A0 r R31 "shReg15" C2 WDE 1 A0 r R32 "shReg16" C2 WDF 1 A0 r R33 "shReg17" C2 WE0 1 A0 r R34 "shReg18" C2 WE1 1 A0 r R35 "shReg19" C2 WE2 1 A0 r R36 "shReg20" C2 WE3 1 A0 r R37 "shReg21" C2 WE4 1 A0 r R38 "shReg22" C2 WE5 1 A0 r R39 "shReg23" C2 WE6 1 A0 r R3A "shReg24" C2 WE7 1 A0 r R3B "shReg25" C2 WE8 1 A0 r R3C "shReg26" C2 WE9 1 A0 r R3D "shReg27" C2 WEA 1 A0 r R3E "shReg28" C2 WEB 1 A0 r R3F "shReg29" C2 WEC 1 A0 r R40 "shReg30" C2 WED 1 A0 r R41 "shReg31" C2 WD6 8 0 W66 W87 W45 W24 W3 WA8 W1 W2 0 CB W0 8 0 W1 32 1 A0 r R5 W2 0 0 W3 0 0 W4 0 0 W5 0 0 W6 0 0 W7 0 0 W8 0 0 W9 0 0 WA 0 0 WB 0 0 WC 0 0 WD 0 0 WE 0 0 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W53 W74 W95 WA6 WAA WAB WBD 8 0 W12 W33 W54 W75 W96 WA6 WAA WAB WBE 8 0 W13 W34 W55 W76 W97 WA6 WAA WAB WBF 8 0 W14 W35 W56 W77 W98 WA6 WAA WAB WC0 8 0 W15 W36 W57 W78 W99 WA6 WAA WAB WC1 8 0 W16 W37 W58 W79 W9A WA6 WAA WAB WC2 8 0 W17 W38 W59 W7A W9B WA6 WAA WAB WC3 8 0 W18 W39 W5A W7B W9C WA6 WAA WAB WC4 8 0 W19 W3A W5B W7C W9D WA6 WAA WAB WC5 8 0 W1A W3B W5C W7D W9E WA6 WAA WAB WC6 8 0 W1B W3C W5D W7E W9F WA6 WAA WAB WC7 8 0 W1C W3D W5E W7F WA0 WA6 WAA WAB WC8 8 0 W1D W3E W5F W80 WA1 WA6 WAA WAB WC9 8 0 W1E W3F W60 W81 WA2 WA6 WAA WAB WCA 8 0 W1F W40 W61 W82 WA3 WA6 WAA WAB WCB 8 0 W20 W41 W62 W83 WA4 WA6 WAA WAB WCC 8 0 W21 W42 W63 W84 WA5 WA6 WAA WAB WAD 1 A0 r R44 "Reg0" CC W0 8 0 W1 0 1 A0 r R5 W2 0 1 A0 r R6 W3 0 1 A0 r R4 W4 0 1 A0 r R3 W5 0 1 A0 r R2 W6 3 1 A0 r R42 W7 0 0 W8 0 0 W9 0 0 WA 0 1 A0 r R0 WB 0 1 A0 r R1 2 A0 r R45 "Reg" A1 a A3 RF 2 W0 WC 6 0 W3 W2 W1 W6 WA WB 0 CD W0 6 0 W1 0 1 A0 r R4 W2 0 1 A0 r R6 W3 0 1 A0 r R5 W4 3 1 A0 r R42 W5 0 0 W6 0 0 W7 0 0 W8 0 1 A0 r R0 W9 0 1 A0 r R1 2 A0 r R46 "RegAndMuxOnly" A1 a AA AbutY RF 3 WA 7 0 W1 W2 W3 W4 W8 W9 WB 0 1 A0 r R47 "muxOut" WC 6 0 WB W7 W2 W1 W9 W8 0 CE W0 6 0 W1 0 2 A4 i 51275 A0 r R14 W2 0 2 A4 i 21973 A0 r R48 "dRead" W3 0 2 A4 i 37044 A0 r R13 W4 0 2 A4 i 26372 A0 r R49 "dOut" W5 0 2 A0 r R1 A4 i 53399 W6 0 2 A0 r R0 A4 i 3184 2 A0 r R4A "Register" A1 a A5 RF 4 W7 7 0 W2 W1 W3 W8 0 0 W4 W6 W5 W9 4 0 W6 W5 W8 W1 0 CF W0 4 0 W1 0 2 A0 r R0 A6 l n W2 0 2 A0 r R1 A6 l n W3 0 2 A0 r R1D A6 l n W4 0 2 A0 r R1E A6 l dw 3 A0 r R1F A7 r R1F A8 lor 1 R20 RF 2 W0 W5 3 0 W3 W1 W4 0 C10 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 dw A0 r R4B "pE(2/3)" R1C pE 2 3 W6 3 0 W3 W4 W2 0 C11 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 dw A0 r R4C "nE(2/3)" R1C nE 2 3 WA 4 0 W6 W5 W1 W8 0 C12 W0 4 0 W1 0 2 A0 r R0 A6 l n W2 0 2 A0 r R1 A6 l n W3 0 2 A0 r R1D A6 l n W4 0 2 A0 r R1E A6 l d 3 A0 r R1F A7 r R1F A8 lor 1 R20 RF 2 W0 W5 3 0 W3 W1 W4 0 C13 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 d A0 r R4D "pE(2/40)" R1C pE 2 40 W6 3 0 W3 W4 W2 0 C14 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 d A0 r R4E "nE(2/16)" R1C nE 2 16 WB 3 0 W2 W3 W4 0 C15 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 1 A0 r R4E R1C nE 2 16 WC 4 0 W6 W5 W8 W3 0 C16 W0 4 0 W1 0 2 A0 r R0 A6 l n W2 0 2 A0 r R1 A6 l n W3 0 2 A0 r R1D A6 l n W4 0 2 A0 r R1E A6 l d 3 A0 r R1F A7 r R1F A8 lor 1 R20 RF 2 W0 W5 3 0 W3 W1 W4 0 C17 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 d A0 r R4F "pE(2/80)" R1C pE 2 80 W6 3 0 W3 W4 W2 0 C18 W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 2 A9 d A0 r R50 "nE(2/32)" R1C nE 2 32 WD 5 0 W8 W6 W1 WB W9 0 C19 W0 5 0 W1 0 2 A4 i 3184 A0 r R0 W2 0 2 A4 i 36980 A0 r R42 W3 0 2 A4 i 65165 A0 r R51 "muxIn" W4 0 2 A4 i 3470 A0 r R47 W5 0 2 A4 i 53399 A0 r R1 2 A0 r R52 "RegMux" A1 a A5 RF 1 W6 5 0 W1 W2 W3 W4 W5 W7 3 0 W2 W3 W4 0 C1A W0 3 0 W1 0 2 A0 r R18 A4 i 47 W2 0 2 A0 r R19 A4 i 834 W3 0 2 A0 r R1A A4 i 834 1 A0 r R53 "nE(2/20)" R1C nE 2 20 WE 5 0 W8 W5 W3 WB W9 0 C19 WD 6 0 W1 W2 W3 W4 W5 W6 0 C1B W0 6 0 W1 0 2 A0 r R5 A4 i 53781 W2 0 2 A0 r R6 A4 i 25334 W3 0 2 A0 r R4 A4 i 25294 W4 0 2 A0 r R3 A4 i 36584 W5 0 2 A0 r R2 A4 i 36582 W6 3 1 A0 r R42 W7 0 1 A4 i 33551 W8 0 1 A4 i 34063 W9 0 1 A4 i 34575 3 A0 r R54 "CreateBuses" AB Reg n 5 A1 a AC CreateBusesLayout RF 0 W0 WAE 1 A0 r R55 "Reg1" CC WAF 1 A0 r R56 "Reg2" CC WB0 1 A0 r R57 "Reg3" CC WB1 1 A0 r R58 "Reg4" CC WB2 1 A0 r R59 "Reg5" CC WB3 1 A0 r R5A "Reg6" CC WB4 1 A0 r R5B "Reg7" CC WB5 1 A0 r R5C "Reg8" CC WB6 1 A0 r R5D "Reg9" CC WB7 1 A0 r R5E "Reg10" CC WB8 1 A0 r R5F "Reg11" CC WB9 1 A0 r R60 "Reg12" CC WBA 1 A0 r R61 "Reg13" CC WBB 1 A0 r R62 "Reg14" CC WBC 1 A0 r R63 "Reg15" CC WBD 1 A0 r R64 "Reg16" CC WBE 1 A0 r R65 "Reg17" CC WBF 1 A0 r R66 "Reg18" CC WC0 1 A0 r R67 "Reg19" CC WC1 1 A0 r R68 "Reg20" CC WC2 1 A0 r R69 "Reg21" CC WC3 1 A0 r R6A "Reg22" CC WC4 1 A0 r R6B "Reg23" CC WC5 1 A0 r R6C "Reg24" CC WC6 1 A0 r R6D "Reg25" CC WC7 1 A0 r R6E "Reg26" CC WC8 1 A0 r R6F "Reg27" CC WC9 1 A0 r R70 "Reg28" CC WCA 1 A0 r R71 "Reg29" CC WCB 1 A0 r R72 "Reg30" CC WCC 1 A0 r R73 "Reg31" CC