DIRECTORY CMosB, CoreClasses, CoreCreate, CoreIO, CoreProperties, Dragon, DragonRosemary, EU2, EU2Arith, EU2Inner, EU2Utils, PadFrame, Ports, PWCore, Rosemary; EU2Impl: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreIO, CoreProperties, DragonRosemary, EU2Arith, EU2Inner, EU2Utils, PadFrame, Ports, PWCore, Rosemary EXPORTS EU2 = BEGIN OPEN EU2, EU2Arith, EU2Utils, CoreCreate; useCachedEU2: BOOL _ FALSE; public: Wire _ GenWiresForBonnie[]; Vdd: PUBLIC NAT _ PortIndex[public, "Vdd"]; Gnd: PUBLIC NAT _ PortIndex[public, "Gnd"]; PadVdd: PUBLIC NAT _ PortIndex[public, "PadVdd"]; PadGnd: PUBLIC NAT _ PortIndex[public, "PadGnd"]; PhA: PUBLIC NAT _ PortIndex[public, "PhA"]; PhB: PUBLIC NAT _ PortIndex[public, "PhB"]; VRef: PUBLIC NAT _ PortIndex[public, "VRef"]; DPRejectB: PUBLIC NAT _ PortIndex[public, "DPRejectB"]; DPData: PUBLIC NAT _ PortIndex[public, "DPData"]; KBus: PUBLIC NAT _ PortIndex[public, "KBus"]; EURes3BisPBus3AB: PUBLIC NAT _ PortIndex[public, "EURes3BisPBus3AB"]; EUWriteToPBus3AB: PUBLIC NAT _ PortIndex[public, "EUWriteToPBus3AB"]; EUAluOp2AB: PUBLIC NAT _ PortIndex[public, "EUAluOp2AB"]; EUCondSel2AB: PUBLIC NAT _ PortIndex[public, "EUCondSel2AB"]; EUCondition2B: PUBLIC NAT _ PortIndex[public, "EUCondition2B"]; DShA: PUBLIC NAT _ PortIndex[public, "DShA"]; DShB: PUBLIC NAT _ PortIndex[public, "DShB"]; DShRd: PUBLIC NAT _ PortIndex[public, "DShRd"]; DShWt: PUBLIC NAT _ PortIndex[public, "DShWt"]; DShIn: PUBLIC NAT _ PortIndex[public, "DShIn"]; DShOut: PUBLIC NAT _ PortIndex[public, "DShOut"]; DHold: PUBLIC NAT _ PortIndex[public, "DHold"]; DStAd: PUBLIC NAT _ PortIndex[public, "DStAd"]; CreateEU2: PUBLIC PROC [ typeData: REF EUTypeData _ NIL, fullEU: BOOL _ FALSE] RETURNS [ cellType: CellType ] = { name: ROPE _ "EU2"; props: Properties _ CoreProperties.Props[[$ClusterInfo, typeData]]; cellType _ SELECT TRUE FROM ~fullEU => CoreClasses.CreateUnspecified[public, name, props], fullEU AND ~useCachedEU2 => CreateFullEU2[props], ENDCASE => CoreIO.RestoreCellType["EU2"]; [] _ Rosemary.SetFixedWire[cellType.public[Vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[Gnd], L]; [] _ Rosemary.SetFixedWire[cellType.public[PadVdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[PadGnd], L]; [] _ Ports.InitPort[cellType.public[DPData], lc, none]; [] _ Ports.InitPort[cellType.public[KBus], lc, none]; [] _ Ports.InitPort[cellType.public[EUAluOp2AB], c, none]; [] _ Ports.InitPort[cellType.public[EUCondition2B], b, drive]; [] _ Ports.InitPort[cellType.public[EUCondSel2AB], c, none]; [] _ Ports.InitPort[cellType.public[DStAd], c, none]; [] _ Ports.InitPort[cellType.public[DShOut], b, drive]; [] _ Rosemary.BindCellType[cellType: cellType, roseClassName: EU2RoseClass]; }; EU2RoseClass: ROPE = Rosemary.Register[roseClassName: "EU2", init: EU2Init, evalSimple: EU2Simple]; EU2Init: Rosemary.InitProc = { state: EU2State _ NEW[EU2StateRec -- [ nRegs ] -- ]; state.data _ NARROW[CoreProperties.GetCellTypeProp[cellType, $ClusterInfo]]; FOR i: NAT IN [0..nRegs) DO state.ram[i] _ 0; ENDLOOP; stateAny _ state; }; EU2Simple: Rosemary.EvalProc = { state: EU2State _ NARROW[stateAny]; {OPEN state; aAdr, bAdr, cAdr: CARD; -- actually, only bytes lSrc, rSrc, stSrc: NAT; st3IsC: BOOL; EUAluLeftSrc1BA: Dragon.ALULeftSources; EUAluRightSrc1BA: Dragon.ALURightSources; EUStore2ASrc1BA: Dragon.Store2ASources; p[KBus].d _ p[DPData].d _ none; IF p[PhA].b THEN { simRegs[cBus] _ IF rejectBA THEN simRegs[r3B] ELSE simRegs[dataIn]; [aAdr, bAdr, cAdr, st3IsC, lSrc, rSrc, stSrc] _ EU2Arith.ExplodeKReg[simRegs[kReg]]; EUStore2ASrc1BA _ VAL[stSrc]; EUAluRightSrc1BA _ VAL[rSrc]; EUAluLeftSrc1BA _ VAL[lSrc]; IF rejectBA THEN cAdr _ marAdr; -- force address IF cAdr # junkAdr THEN { IF data # NIL AND data.noteStore # NIL AND NOT data.storeNoted THEN { data.noteStore[data: data.data, reg: cAdr, value: simRegs[cBus]]; data.storeNoted _ TRUE; }; SELECT cAdr FROM IFUAdr => {p[KBus].d _ drive; p[KBus].lc _ simRegs[cBus]}; IN [stackAdr .. bogusAdr) => ram[cAdr] _ simRegs[cBus]; ENDCASE => DragonRosemary.Assert[FALSE, "EU cAdr out of range"]; IF cAdr=fieldAdr THEN simRegs[field] _ simRegs[cBus]; }; IF ~rejectBA AND ~conditionBA THEN carryAB _ carryBA; IF ~rejectBA THEN { simRegs[left] _ SELECT EUAluLeftSrc1BA FROM aBus => ram[aAdr], rBus => simRegs[r2B], cBus => simRegs[cBus], ENDCASE => ERROR; simRegs[right] _ SELECT EUAluRightSrc1BA FROM bBus => ram[bAdr], rBus => simRegs[r2B], cBus => simRegs[cBus], kBus => p[KBus].lc, fCtlReg => simRegs[field], ENDCASE => ERROR; simRegs[st2A] _ SELECT EUStore2ASrc1BA FROM bBus => ram[bAdr], cBus => simRegs[cBus], rBus => simRegs[r2B], ENDCASE => ERROR; simRegs[r3A] _ simRegs[r2B]; simRegs[st3A] _ IF st3IsC THEN simRegs[cBus] ELSE simRegs[st2B]; p[DPData].d _ drive; -- Send address to Cache only once: the cache latches it. p[DPData].lc _ simRegs[r2B]; }; } ELSE IF data # NIL THEN data.storeNoted _ FALSE; IF p[PhB].b THEN { aluOut, fuOut: CARD; -- temporary overflow, c32, lz, ez, il: BOOL; aluOps: Dragon.ALUOps _ VAL[p[EUAluOp2AB].c]; rejectBA _ p[DPRejectB].b; simRegs[kReg] _ p[KBus].lc; DragonRosemary.Assert[NOT (p[EUWriteToPBus3AB].b AND p[EURes3BisPBus3AB].b)]; simRegs[r3B] _ simRegs[r3A]; -- copy address simRegs[dataIn] _ p[DPData].lc; -- latch whatever comes form the pads IF p[EUWriteToPBus3AB].b THEN { -- store in progress: sending data p[DPData].d _ drive; p[DPData].lc _ simRegs[st3A] -- send data to Cache (Store) }; simRegs[st2B] _ simRegs[st2A]; [aluOut, c32, carryBA] _ EU2Arith.ALUOperation[aluOps, simRegs[left], simRegs[right], carryAB]; fuOut _ IF aluOps=FOP THEN FieldOp[simRegs[left], simRegs[st2A], simRegs[right]] ELSE 0; simRegs[r2B] _ SELECT aluOps FROM BndChk => simRegs[left], FOP => fuOut, ENDCASE => aluOut; overflow _ ((c32 # EBFLC[aluOut, 0]) # (EBFLC[simRegs[left], 0] # EBFLC[simRegs[right], 0])); lz _ (c32#(EBFLC[simRegs[left], 0]#EBFLC[simRegs[right], 0])); ez _ aluOut=0; il _ LispTest[simRegs[left]] OR LispTest[simRegs[right]] OR LispTest[aluOut]; conditionBA _ SELECT Dragon.CondSelects[VAL[p[EUCondSel2AB].c]] FROM False => FALSE, EZ => ez, LZ => lz, -- VSub<0 LE => ez OR lz, -- VSub<=0, AddressCheckFault => aluOut < KernalLimit, NE => ~ez, GE => ~lz, -- VSub>=0 GZ => ~(ez OR lz), -- VSub>0, OvFl => overflow, BC => ~c32, IL => il, -- the 3 high-order bits must be the same for both operands and result NotBC => c32, NotIL => ~il, ModeFault => TRUE, ENDCASE => ERROR Rosemary.Stop["Invalid EUCondition2B Code"]; p[EUCondition2B].b _ conditionBA; }; }}; globalPos: NAT _ 0; -- add the increment, then put the pad SetFirst: PROC [pos: NAT] = {globalPos _ pos}; Next: PROC [] RETURNS [NAT] = {RETURN[Move[1]]}; Move: PROC [delta: NAT] RETURNS [NAT] = { globalPos _ globalPos+delta; RETURN[globalPos]}; CreateFullEU2: PROC [props: Properties _ NIL] RETURNS [cellType: CellType] = { vSize: NAT = 41; hSize: NAT = 50; left: NAT = 0; bottom: NAT = left+vSize; -- 41 right: NAT = bottom+hSize; -- 91 top: NAT = right+vSize; -- 132 iL: CellInstances _ LIST [Instance[PWCore.RotateCellType[EU2Inner.CreateEU2Inner[], $Rot90]]]; SetFirst[left+10]; iL _ PadFrame.AddPad[iL, "DShA", $In, Next[], ["toChip", "shiftA"]]; -- new: 11 iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, "DShB", $In, Next[], ["toChip", "shiftB"]]; iL _ PadFrame.AddPad[iL, "DShRd", $In, Next[], ["toChip", "read"]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, "DShWt", $In, Next[], ["toChip", "write"]]; iL _ PadFrame.AddPad[iL, "DShIn", $In, Next[], ["toChip", "shIn"]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]]; iL _ PadFrame.AddPad[iL, "DShOut", $Out, Next[], ["fromChip", "shOut"]]; iL _ PadFrame.AddPad[iL, "DHold", $In, Next[], ["toChip", "hold"]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]]; iL _ PadFrame.AddPad[iL, public[DStAd][0], $In, Next[], ["toChip", "dStateAd[0]"]]; iL _ PadFrame.AddPad[iL, public[DStAd][1], $In, Next[], ["toChip", "dStateAd[1]"]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]]; iL _ PadFrame.AddPad[iL, public[DStAd][2], $In, Next[], ["toChip", "dStateAd[2]"]]; iL _ PadFrame.AddPad[iL, public[DStAd][3], $In, Next[], ["toChip", "dStateAd[3]"]]; iL _ PadFrame.AddPad[iL, NIL, $Copyright, Next[]]; iL _ PadFrame.AddPad[iL, NIL, $Logo, Next[]]; iL _ PadFrame.AddPad[iL, NIL, $Name, Next[]]; SetFirst[bottom]; -- 41 FOR i: NAT IN [0..16) DO index: NAT _ 31-2*i; iL _ PadFrame.AddPad[iL, public[DPData][index], $IOTst, Move[2], -- s on 43 ["toChip", Index["fromPBus", index]], ["fromChip", Index["toPBus", index]], ["enWA", "enWrtPBusPhA"], ["enWB", "enWrtPBusPhB"]]; iL _ PadFrame.AddPad[iL, public[DPData][index-1], $IOTst, Next[], -- s on 44 ["toChip", Index["fromPBus", index-1]], ["fromChip", Index["toPBus", index-1]], ["enWA", "enWrtPBusPhA"], ["enWB", "enWrtPBusPhB"]]; ENDLOOP; SetFirst[bottom]; -- 42 iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; -- v on 42 iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; SetFirst[right+8]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; -- v on 100 iL _ PadFrame.AddPad[iL, "DPRejectB", $In, Next[], ["toChip", "reject"]]; iL _ PadFrame.AddPad[iL, "PhA", $Clk, Next[], ["Clock", "phA"], ["nClock", "nPhA"]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, "PhB", $Clk, Next[], ["Clock", "phB"], ["nClock", "nPhB"]]; iL _ PadFrame.AddPad[iL, "VRef", $Analog, Next[]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, "EUCondition2B", $Out, Next[], ["fromChip", "condition"]]; iL _ PadFrame.AddPad[iL, "EURes3BisPBus3AB", $In, Next[], ["toChip", "res3BisP"]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]]; iL _ PadFrame.AddPad[iL, "EUWriteToPBus3AB", $In, Next[], ["toChip", "writePBus"]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][0], $In, Next[], ["toChip", "aluOp[0]"]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][1], $In, Next[], ["toChip", "aluOp[1]"]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][2], $In, Next[], ["toChip", "aluOp[2]"]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][3], $In, Next[], ["toChip", "aluOp[3]"]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][0], $In, Next[], ["toChip", "condSel[0]"]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][1], $In, Next[], ["toChip", "condSel[1]"]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][2], $In, Next[], ["toChip", "condSel[2]"]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][3], $In, Next[], ["toChip", "condSel[3]"]]; SetFirst[top]; -- 132 FOR i: NAT IN [0..16) DO index: NAT _ 31-2*i; iL _ PadFrame.AddPad[iL, public[KBus][index], $IOTst, Move[2], -- s on 134 ["toChip", Index["fromIFU", index]], ["fromChip", Index["toIFU", index]], ["enWA", "enWrtIFUPhA"], ["enWB", "enWrtIFUPhB"]]; iL _ PadFrame.AddPad[iL, public[KBus][index-1], $IOTst, Next[], -- s on 135 ["toChip", Index["fromIFU", index-1]], ["fromChip", Index["toIFU", index-1]], ["enWA", "enWrtIFUPhA"], ["enWB", "enWrtIFUPhB"]]; ENDLOOP; SetFirst[top]; -- 132 iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; -- v on 133 iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; cellType _ Cell[name: "EU2", public: public, onlyInternal: GenWiresForOnion[], instances: iL, props: props]; PWCore.SetLayout[cellType, $PadFrame, PadFrame.padFrameParamsProp, NEW[PadFrame.PadFrameParametersRec _ [ nbPadsX: hSize, nbPadsY: vSize, horizLayer: "metal2", vertLayer: "metal", centerDisplacement: [-200*CMosB.lambda, 0]]]]; }; END. DEU2Impl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Louis Monier June 17, 1986 8:06:14 pm PDT McCreight, May 12, 1986 12:23:08 pm PDT Bertrand Serlet June 15, 1986 0:57:35 am PDT Barth, April 19, 1986 5:25:00 pm PST Last Edited by: Louis Monier June 22, 1986 11:49:26 pm PDT 2 bits {aBus(0), rBus(1), cBus(2), reserve3(3)} 3 bits {bBus(0), rBus(1), cBus(2), kBus(3), fCtlReg(4)} 2 bits {bBus(0), rBus(1), cBus(2), reserve3(3)} -- PhA phase. Note that rejectBA alone inhibits almost any state change during PhA -- Better be first! We use the latched version of reject here, so no race. -- Updating the RAM addresses and various control bits; notice the role of reject -- On every PhA with RejectBA the faulty address is saved in ram[euMAR]; the EU generates the appropriate cAdr when RejectBA is sensed, so the rule is: we always write into the register file! -- PhiB phase. Most of the computations take place during PhB DPRejectB is valid at the end of PhiB but bogus on PhiA, so it must be latched by PhiB. -- Receive RAM addresses and control bits on KBus form IFU -- PBus: notice that in case of reject during a store, we keep sending the data even though it is useless -- In case of a fetch, an op, or a move, we are done -- Data pipe -- ALU computation -- FU computation -- Now pick up the result -- Condition and trap generation -- Left side -- Bottom side -- Right side -- Top side -- The first version, with a large square pad frame; don't touch!!! CreateSquareEU2: PROC [props: Properties _ NIL] RETURNS [cellType: CellType] = { vSize: NAT = 52; hSize: NAT = 52; left: NAT = 0; bottom: NAT = left+vSize; right: NAT = bottom+hSize; top: NAT = right+vSize; iL: CellInstances _ LIST [Instance[PWCore.RotateCellType[EU2Inner.CreateEU2Inner[], $Rot90]]]; -- Left side SetFirst[15]; iL _ PadFrame.AddPad[iL, "DShA", $In, Next[], ["toChip", "shiftA"]]; -- on 16 iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, "DShB", $In, Next[], ["toChip", "shiftB"]]; iL _ PadFrame.AddPad[iL, "DShRd", $In, Next[], ["toChip", "read"]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, "DShWt", $In, Next[], ["toChip", "write"]]; iL _ PadFrame.AddPad[iL, "DShIn", $In, Next[], ["toChip", "shIn"]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]]; iL _ PadFrame.AddPad[iL, "DShOut", $Out, Next[], ["fromChip", "shOut"]]; iL _ PadFrame.AddPad[iL, "DHold", $In, Next[], ["toChip", "hold"]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]]; iL _ PadFrame.AddPad[iL, public[DStAd][0], $In, Next[], ["toChip", "dStateAd[0]"]]; iL _ PadFrame.AddPad[iL, public[DStAd][1], $In, Next[], ["toChip", "dStateAd[1]"]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]]; iL _ PadFrame.AddPad[iL, public[DStAd][2], $In, Next[], ["toChip", "dStateAd[2]"]]; iL _ PadFrame.AddPad[iL, public[DStAd][3], $In, Next[], ["toChip", "dStateAd[3]"]]; iL _ PadFrame.AddPad[iL, NIL, $Copyright, Next[]]; iL _ PadFrame.AddPad[iL, NIL, $Logo, Next[]]; iL _ PadFrame.AddPad[iL, NIL, $Name, Next[]]; -- Bottom side SetFirst[bottom+1]; FOR i: NAT IN [0..16) DO index: NAT _ 31-2*i; iL _ PadFrame.AddPad[iL, public[DPData][index], $IOTst, Move[2], ["toChip", Index["fromPBus", index]], ["fromChip", Index["toPBus", index]], ["enWA", "enWrtPBusPhA"], ["enWB", "enWrtPBusPhB"]]; iL _ PadFrame.AddPad[iL, public[DPData][index-1], $IOTst, Next[], ["toChip", Index["fromPBus", index-1]], ["fromChip", Index["toPBus", index-1]], ["enWA", "enWrtPBusPhA"], ["enWB", "enWrtPBusPhB"]]; ENDLOOP; SetFirst[bottom]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; -- Right side SetFirst[117]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; -- 118 iL _ PadFrame.AddPad[iL, "DPRejectB", $In, Next[], ["toChip", "reject"]]; iL _ PadFrame.AddPad[iL, "PhA", $Clk, Next[], ["Clock", "phA"], ["nClock", "nPhA"]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, "PhB", $Clk, Next[], ["Clock", "phB"], ["nClock", "nPhB"]]; iL _ PadFrame.AddPad[iL, "VRef", $Analog, Next[]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, "EUCondition2B", $Out, Next[], ["fromChip", "condition"]]; iL _ PadFrame.AddPad[iL, "EURes3BisPBus3AB", $In, Next[], ["toChip", "res3BisP"]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]]; iL _ PadFrame.AddPad[iL, "EUWriteToPBus3AB", $In, Next[], ["toChip", "writePBus"]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][0], $In, Next[], ["toChip", "aluOp[0]"]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][1], $In, Next[], ["toChip", "aluOp[1]"]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][2], $In, Next[], ["toChip", "aluOp[2]"]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUAluOp2AB][3], $In, Next[], ["toChip", "aluOp[3]"]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][0], $In, Next[], ["toChip", "condSel[0]"]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][1], $In, Next[], ["toChip", "condSel[1]"]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][2], $In, Next[], ["toChip", "condSel[2]"]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, public[EUCondSel2AB][3], $In, Next[], ["toChip", "condSel[3]"]]; -- Top side SetFirst[top+1]; -- first at 159 FOR i: NAT IN [0..16) DO index: NAT _ 31-2*i; iL _ PadFrame.AddPad[iL, public[KBus][index], $IOTst, Move[2], ["toChip", Index["fromIFU", index]], ["fromChip", Index["toIFU", index]], ["enWA", "enWrtIFUPhA"], ["enWB", "enWrtIFUPhB"]]; iL _ PadFrame.AddPad[iL, public[KBus][index-1], $IOTst, Next[], ["toChip", Index["fromIFU", index-1]], ["fromChip", Index["toIFU", index-1]], ["enWA", "enWrtIFUPhA"], ["enWB", "enWrtIFUPhB"]]; ENDLOOP; SetFirst[top]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Next[]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "Gnd", $Gnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadGnd", $PadGnd, Move[3]]; iL _ PadFrame.AddPad[iL, "PadVdd", $PadVdd, Move[3]]; iL _ PadFrame.AddPad[iL, "Vdd", $Vdd, Next[]]; cellType _ Cell[name: "EU2", public: public, onlyInternal: GenWiresForOnion[], instances: iL, props: props]; PWCore.SetLayout[cellType, $PadFrame, PadFrame.padFrameParamsProp, NEW[PadFrame.PadFrameParametersRec _ [nbPadsX: hSize, nbPadsY: vSize, horizLayer: "metal2", vertLayer: "metal"]]]; }; Κƒ– "cedar" style˜codešœ ™ Kšœ Οmœ1™˜>Kšœžœ'˜1Kšžœ"˜)—Kšœ4˜4Kšœ4˜4Kšœ7˜7Kšœ7˜7Kšœ7˜7Kšœ5˜5Kšœ:˜:Kšœ>˜>Kšœ<˜Jšœ˜Jšœžœžœ˜Mšœžœžœž˜DJšœ žœ˜Jšžœ ˜ Jšžœ ‘ ˜Jšžœ žœ‘ ˜Jšœ*˜*Jšžœ ˜ Jšžœ ‘ ˜Jšžœ žœ‘ ˜Jšœ˜Jšžœ ˜Jšžœ ‘F˜RJšœ˜Jšœ˜Jšœžœ˜Jšžœžœ-˜=—Jšœ!˜!Jšœ˜—Kšœ˜—K˜Kšœ žœ‘&˜:Kš œžœžœ˜.Kš  œžœžœžœžœ ˜0š  œžœ žœžœžœ˜)Kšœ˜Kšžœ ˜K˜—š  œžœžœžœ˜NKšœžœ˜Kšœžœ˜Kšœžœ˜Kšœžœ‘˜Kšœžœ‘˜ Kšœžœ‘˜KšœžœF˜^K™ Kšœ˜KšœE‘ ˜OKšœ.˜.KšœD˜DKšœC˜CKšœ4˜4KšœD˜DKšœC˜CKšœ4˜4KšœH˜HKšœC˜CKšœ.˜.KšœS˜SKšœS˜SKšœ.˜.KšœS˜SKšœS˜SKšœžœ˜2Kšœžœ˜-Kšœžœ˜-K™K™Kšœ‘˜šžœžœžœ ž˜Kšœžœ ˜šœB‘ ˜LKšœ&˜&Kšœ%˜%Kšœ˜Kšœ˜—šœC‘ ˜MKšœ(˜(Kšœ'˜'Kšœ˜Kšœ˜—Kšžœ˜—Kšœ‘˜Kšœ1‘ ˜;Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ/˜/K™K™ Kšœ˜Kšœ6‘ ˜AKšœI˜IKšœT˜TKšœ.˜.KšœT˜TKšœ2˜2Kšœ4˜4KšœS˜SKšœR˜RKšœ4˜4KšœS˜SKšœU˜UKšœ.˜.KšœU˜UKšœU˜UKšœ4˜4KšœU˜UKšœY˜YKšœ4˜4KšœY˜YKšœY˜YKšœ.˜.KšœY˜YK™K™ Kšœ‘˜šžœžœžœ ž˜Kšœžœ ˜šœ@‘ ˜KKšœ%˜%Kšœ$˜$Kšœ˜Kšœ˜—šœA‘ ˜LKšœ'˜'Kšœ&˜&Kšœ˜Kšœ˜—Kšžœ˜—Kšœ‘˜Kšœ0‘ ˜;Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ5˜5Kšœ/˜/Kšœ5˜5Kšœ/˜/K˜šœ˜Kšœ˜Kšœ!˜!Kšœ˜Kšœ˜—šœCžœ#˜iKšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ.˜.—Kšœ˜K˜—K™Cš œžœžœžœ™PKšœžœ™Kšœžœ™Kšœžœ™Kšœžœ™Kšœžœ™Kšœžœ™KšœžœF™^K™ Kšœ ™ KšœE‘™MKšœ.™.KšœD™DKšœC™CKšœ4™4KšœD™DKšœC™CKšœ4™4KšœH™HKšœC™CKšœ.™.KšœS™SKšœS™SKšœ.™.KšœS™SKšœS™SKšœžœ™2Kšœžœ™-Kšœžœ™-K™K™Kšœ™šžœžœžœ ž™Kšœžœ ™šœA™AKšœ&™&Kšœ%™%Kšœ™Kšœ™—šœB™BKšœ(™(Kšœ'™'Kšœ™Kšœ™—Kšžœ™—Kšœ™Kšœ.™.Kšœ4™4Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ.™.K™K™ Kšœ™Kšœ5‘™;KšœI™IKšœT™TKšœ.™.KšœT™TKšœ2™2Kšœ4™4KšœS™SKšœR™RKšœ4™4KšœS™SKšœU™UKšœ.™.KšœU™UKšœU™UKšœ4™4KšœU™UKšœY™YKšœ4™4KšœY™YKšœY™YKšœ.™.KšœY™YK™K™ Kšœ‘™ šžœžœžœ ž™Kšœžœ ™šœ?™?Kšœ%™%Kšœ$™$Kšœ™Kšœ™—šœ@™@Kšœ'™'Kšœ&™&Kšœ™Kšœ™—Kšžœ™—Kšœ™Kšœ.™.Kšœ4™4Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ/™/Kšœ5™5Kšœ5™5Kšœ.™.K™šœ™Kšœ™Kšœ!™!Kšœ™Kšœ™—KšœCžœo™΅Kšœ™K™—K˜Kšžœ˜K˜—…—3–c]