DIRECTORY CoreCreate, EU2DP, EU2LeafUtils, EU2Utils, Rosemary, Ports;

EU2DPImpl: CEDAR PROGRAM
IMPORTS CoreCreate, EU2LeafUtils, EU2Utils, Rosemary, Ports 
EXPORTS EU2DP = 
BEGIN OPEN CoreCreate, EU2DP, EU2Utils;

public: Wire _ Union[
GenPGnEWires[],	-- NO clocks
GenWiresDPToPads[], 
GenWiresForRouter[]];
Vdd: PUBLIC NAT _ PortIndex[public, "Vdd"];
Gnd: PUBLIC NAT _ PortIndex[public, "Gnd"];
fromIFU: PUBLIC NAT _ PortIndex[public, "fromIFU"];
toIFU: PUBLIC NAT _ PortIndex[public, "toIFU"];
toPBus: PUBLIC NAT _ PortIndex[public, "toPBus"];
fromPBus: PUBLIC NAT _ PortIndex[public, "fromPBus"];
ramAdr: PUBLIC NAT _ PortIndex[public, "ramAdr"];
selA: PUBLIC NAT _ PortIndex[public, "selA"];
selB: PUBLIC NAT _ PortIndex[public, "selB"];
selC: PUBLIC NAT _ PortIndex[public, "selC"];
selALow: PUBLIC NAT _ PortIndex[public, "selALow"];
selBLow: PUBLIC NAT _ PortIndex[public, "selBLow"];
selCLow: PUBLIC NAT _ PortIndex[public, "selCLow"];
dRamRead: PUBLIC NAT _ PortIndex[public, "dRamRead"];
leftSrc: PUBLIC NAT _ PortIndex[public, "leftSrc"];
rightSrc: PUBLIC NAT _ PortIndex[public, "rightSrc"];
st2ASrc: PUBLIC NAT _ PortIndex[public, "st2ASrc"];
loadField: PUBLIC NAT _ PortIndex[public, "loadField"];
zero: PUBLIC NAT _ PortIndex[public, "zero"];
carryOut: PUBLIC NAT _ PortIndex[public, "carryOut"];
res: PUBLIC NAT _ PortIndex[public, "res"];
opL: PUBLIC NAT _ PortIndex[public, "opL"];
opR: PUBLIC NAT _ PortIndex[public, "opR"];
fd: PUBLIC NAT _ PortIndex[public, "fd"];
insertFd: PUBLIC NAT _ PortIndex[public[fd], "insertFd"];
maskFd: PUBLIC NAT _ PortIndex[public[fd], "maskFd"];
shiftFd: PUBLIC NAT _ PortIndex[public[fd], "shiftFd"];
pipeRegsSel: PUBLIC NAT _ PortIndex[public, "pipeRegsSel"];
dRead: PUBLIC NAT _ PortIndex[public[pipeRegsSel][0], "dRead"];
sel: PUBLIC NAT _ PortIndex[public[pipeRegsSel][0], "sel"];
carryIn: PUBLIC NAT _ PortIndex[public, "carryIn"];
op: PUBLIC NAT _ PortIndex[public, "op"];
insert: PUBLIC NAT _ PortIndex[public, "insert"];
mask: PUBLIC NAT _ PortIndex[public, "mask"];
shift: PUBLIC NAT _ PortIndex[public, "shift"];
sh: PUBLIC NAT _ PortIndex[public, "sh"];


CreateEU2DataPath: PUBLIC PROC RETURNS [cellType: CellType] = {
cellType _ EU2LeafUtils.Extract["EU2DataPath.sch"];

[] _ Rosemary.SetFixedWire[cellType.public[Vdd], H];
[] _ Rosemary.SetFixedWire[cellType.public[Gnd], L];
[] _ Ports.InitPort[cellType.public[fromIFU], lc, none];
[] _ Ports.InitPort[cellType.public[toIFU], lc, drive];
[] _ Ports.InitPort[cellType.public[toPBus], lc, drive];
[] _ Ports.InitPort[cellType.public[fromPBus], lc, none];
FOR i: NAT IN [a..c] DO
[] _ Ports.InitPort[cellType.public[ramAdr][i][hi], c, drive];
[] _ Ports.InitPort[cellType.public[ramAdr][i][low], c, drive];
ENDLOOP;
InitLeafPorts[cellType.public[selA], none];
InitLeafPorts[cellType.public[selB], none];
InitLeafPorts[cellType.public[selC], none];
InitLeafPorts[cellType.public[selALow], none];
InitLeafPorts[cellType.public[selBLow], none];
InitLeafPorts[cellType.public[selCLow], none];
[] _ Ports.InitPort[cellType.public[leftSrc], c, drive];
[] _ Ports.InitPort[cellType.public[rightSrc], c, drive];
[] _ Ports.InitPort[cellType.public[st2ASrc], c, drive];
[] _ Ports.InitPort[cellType.public[loadField], b, drive];
[] _ Ports.InitPort[cellType.public[zero], b, drive];
[] _ Ports.InitPort[cellType.public[carryOut], b, drive];
[] _ Ports.InitPort[cellType.public[res], c, drive];
[] _ Ports.InitPort[cellType.public[opL], c, drive];
[] _ Ports.InitPort[cellType.public[opR], c, drive];
[] _ Ports.InitPort[cellType.public[fd], c, drive];	-- fix it!!!

[] _ Rosemary.BindCellType[cellType: cellType, roseClassName: EU2DPClass];
};

EU2DPClass: ROPE = Rosemary.Register[roseClassName: "EU2DP", evalSimple: EU2DPSimple];
EU2DPSimple: Rosemary.EvalProc = {};

END.

EU2DPSimple: Rosemary.EvalProc = {
}};

���	��EU2DPImpl.mesa
Copyright c 1985 by Xerox Corporation.  All rights reserved.
Louis Monier March 18, 1986 2:02:59 am PST
Bertrand Serlet March 31, 1986 2:25:40 pm PST
-- PGE
-- from and to pad frame
-- to RAM control
-- from RAM control to RAM
-- to control
-- from control
	TO DO
state: EU2DPState _ NARROW[stateAny];
{OPEN state;
SetReg: PROC [reg: PipeRange] ~ {
source: SourceRange;
found: BOOL _ FALSE;
FOR i: NAT IN [0..sources[reg].sizeSel) DO
IF p[pipeRegsSel][reg][sel][i].b THEN 	-- if a select line is up
{IF found THEN ERROR;	-- and not two select lines are high
source _ sources[reg].inputs[i];
simRegs[reg] _ simRegs[source];	-- then update the value
found _ TRUE};
ENDLOOP;
};

aAdr, bAdr, cAdr, aR, bR, cR: NAT;
l, r: CARD;

-- Compute peudo-states first
-- read the RAM
aAdr _ p[selA].c*4+p[selALow].c; 
bAdr _ p[selB].c*4+p[selBLow].c; 
simRegs[ramA] _ ram[aAdr];
simRegs[ramB] _ ram[bAdr];
-- read input ports
simRegs[ifuIn] _ p[fromIFU].lc;	-- maybe an immediate operand from the IFU
simRegs[pIn] _ p[toPBus].lc;	-- data back from the Cache, or junk
-- alu computation
l _ simRegs[left];
r _ simRegs[right];
IF p[aluCtrl][invB].b THEN r _ WordNot[r];
SELECT TRUE FROM
p[aluCtrl][add].b => [simRegs[aluOut], p[ccIn][c32].b] _ 
DoubleADD[l, r, p[aluCtrl][carryIn].b];
p[aluCtrl][and].b => simRegs[aluOut] _ WordAnd[l, r]; 
p[aluCtrl][or].b => simRegs[aluOut] _ WordOr[l, r]; 
p[aluCtrl][xor].b => simRegs[aluOut] _ WordXor[l, r]; 
ENDCASE => ERROR;
-- fu computation
simRegs[fuOut] _ FieldOp[simRegs[left], simRegs[st2A], simRegs[right]];

-- Update the States
-- ram: always write
cAdr _ p[selC].c*4+p[selCLow].c; 
IF cAdr IN [stackAdr .. bogusAdr] THEN ram[cAdr] _ simRegs[cBus];
-- pipeline registers
FOR reg: PipeRange IN PipeRange DO SetReg[reg] ENDLOOP;
-- Drive output ports to control
-- drive ramAdr, leftSrc, rightSrc, st2ASrc and loadField
[aR, bR, cR, p[loadField].b, p[leftSrc].c, p[rightSrc].c, p[st2ASrc].c] 
_ ExplodeKReg[simRegs[kReg]];
p[ramAdr][a][hi].c _ aR/4;
p[ramAdr][a][low].c _ aR MOD 4;
p[ramAdr][b][hi].c _ bR/4;
p[ramAdr][b][low].c _ bR MOD 4;
p[ramAdr][c][hi].c _ cR/4;
p[ramAdr][c][low].c _ cR MOD 4;
-- drive ccIn
p[ccIn][zero].b _ simRegs[r2B]=0;
p[ccIn][res].c _ simRegs[r2B]/4000000000B;	-- probably wrong!!!
p[ccIn][opL].c _ simRegs[left]/4000000000B;
p[ccIn][opR].c _ simRegs[right]/4000000000B;

-- Drive output ports to pads
p[toIFU].lc _ simRegs[cBus];				-- cBus, ev. for IFU
p[toPBus].lc _ simRegs[pDriver];		-- adr or data for Cache
�ÊU��–

"cedar" style˜�
codeš
œ™Kšœ
Ïm
œ1™<K™*K™-—K˜�KšÏk	œ<˜EK˜�•StartOfExpansion[]šÏb	œžœ
ž˜Kšžœ5˜<Kšžœ	˜Kšžœ
žœ˜'—K˜�š
œ˜KšœÏc˜Kš
œ˜Kš
œ˜—Kš
œ™Kšœžœ
žœ˜+Kšœžœ
žœ˜+K™Kšœ	žœ
žœ ˜3Kšœžœ
žœ˜/Kšœžœ
žœ˜1Kšœ
žœ
žœ!˜5K™Kšœžœ
žœ˜1K™Kšœžœ
žœ˜-Kšœžœ
žœ˜-Kšœžœ
žœ˜-Kšœ	žœ
žœ ˜3Kšœ	žœ
žœ ˜3Kšœ	žœ
žœ ˜3Kšœ
žœ
žœ!˜5K™
Kšœ	žœ
žœ ˜3Kšœ
žœ
žœ!˜5Kšœ	žœ
žœ ˜3Kšœžœ
žœ"˜7Kšœžœ
žœ˜-Kšœ
žœ
žœ!˜5Kšœžœ
žœ˜+Kšœžœ
žœ˜+Kšœžœ
žœ˜+šœžœ
žœ˜)Kšœ
žœ
žœ%˜9Kšœžœ
žœ#˜5Kšœ	žœ
žœ$˜7—K™šœ
žœ
žœ$˜;Kšœžœ
žœ.˜?Kšœžœ
žœ,˜;—Kšœ	žœ
žœ ˜3Kšœžœ
žœ˜)Kšœžœ
žœ˜1Kšœžœ
žœ˜-Kšœžœ
žœ˜/Kšœžœ
žœ˜)K˜�K˜�šÏnœžœ
žœ˜?Kš
œ3˜3K˜�Kš
œ4˜4Kš
œ4˜4Kš
œ8˜8Kš
œ7˜7Kš
œ8˜8Kš
œ9˜9šžœžœ
žœž˜Kš
œ>˜>Kš
œ?˜?Kšžœ
˜—Kš
œ+˜+Kš
œ+˜+Kš
œ+˜+Kš
œ.˜.Kš
œ.˜.Kš
œ.˜.Kš
œ8˜8Kš
œ9˜9Kš
œ8˜8Kš
œ:˜:Kš
œ5˜5Kš
œ9˜9Kš
œ4˜4Kš
œ4˜4Kš
œ4˜4Kšœ4 ˜@K˜�Kš
œJ˜JKš
œ˜—K˜�KšœžœF˜VKšŸœ˜$K˜�Kšžœ
˜Kš
Ðbl™K˜�šŸœ˜"Kšœžœ™%Jšœ
žœ™š¡œžœ™!Kš
œ™Kšœžœžœ
™šžœžœ
žœž™*šžœžœ ™@Kšœ
žœžœ
žœ $™:Kš
œ ™ Kšœ  ™8Kšœžœ™—Kšžœ
™—J™—J™�Jšœžœ
™"Jšœžœ
™J™�™™Kš
œ!™!Kš
œ!™!Kš
œ™Kš
œ™—™Kšœ# '™JKšœ $™A—™Kš
œ™Kš
œ™Kšžœžœ™*šžœ
žœ
ž™š
œ9™9Kš
œ'™'—Kš
œ6™6Kš
œ4™4Kš
œ6™6Kšžœžœ
™——™Jš
œG™GJ™�——™™Kš
œ!™!Kšžœžœžœ™A—™Kšžœžœžœ
žœ
™7——™ š
œ9™9š
œH™HJš
œ™—Jš
œ™Jšœžœ™Jš
œ™Jšœžœ™Jš
œ™Jšœžœ™—™
Jš
œ!™!Jšœ+ ™?Jš
œ+™+Jš
œ,™,——J™�™Jšœ  ™4Jšœ" ™:—Kš
œ˜—K˜�—�…—����ò��	��