DIRECTORY Core, EU2Arith, EU2Utils; EU2DP: CEDAR DEFINITIONS = BEGIN OPEN EU2Arith, EU2Utils; Vdd, Gnd: NAT; -- in fromIFU: NAT; -- in from pads toIFU: NAT; -- out to pads during A toPBus: NAT; -- out to pads any time fromPBus: NAT; -- in B from pads ramAdr: NAT; -- ramAdr[0..3)[Hi[0..6), Low[0..2)] selA, selB, selC, selALow, selBLow, selCLow: NAT; -- 2AB dRamRead: NAT; leftSrc, rightSrc, st2ASrc, loadField: NAT; -- out to control during 1BA zero, carryOut, res, opL, opR: NAT; -- out to control during 2AB fd: NAT; -- out to control during 2AB insertFd, maskFd, shiftFd: NAT; pipeRegsSel: NAT; -- in dRead, sel: NAT; carryIn, op: NAT; -- in insert, mask, shift, sh: NAT; -- in EU2DPState: TYPE = REF EU2DPStateRec; EU2DPStateRec: TYPE = RECORD[ simRegs: ARRAY SourceRange OF CARD, -- some of them are not states ram: ARRAY [0..nbWords) OF CARD]; CreateEU2DataPath: PROC RETURNS [Core.CellType]; END. δEU2DP.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Louis Monier March 18, 1986 0:57:36 am PST -- PGE -- from and to pad frame -- to RAM control -- from RAM control to RAM -- to control -- from kReg register -- from ALU -- from right register -- from control -- registers -- alu -- field unit -- registers -- register file -- distributed inside simRegs[kReg] aAdr, bAdr, cAdr: CARD, -- actually, only bytes cIsField: BOOL, EUAluLeftSrc1BA: Dragon.ALULeftSources, -- 2 bits {aBus(0), rBus(1), cBus(2), reserve3(3)} EUAluRightSrc1BA: Dragon.ALURightSources, -- 3 bits {bBus(0), rBus(1), cBus(2), kBus(3), fCtlReg(4)} EUStore2ASrc1BA: Dragon.Store2ASources, -- 2 bits {bBus(0), rBus(1), cBus(2), reserve3(3)} Κ;˜šœ ™ Icodešœ Οmœ1™