[Indigo]<Dragon>EU2>EU2TopImpl.mesa!5

EU2TopImpl.mesa

Louis Monier January 29, 1986 5:17:36 pm PST

Bertrand Serlet January 17, 1986 11:49:08 am PST

DIRECTORY CoreCreate, CoreOps, EU2ALU, EU2RamControl, EU2DPControl, EU2FU, EU2Ram, EU2Regs, EU2Top, EU2Utils;

EU2TopImpl: CEDAR PROGRAM

IMPORTS CoreCreate, CoreOps, EU2ALU, EU2RamControl, EU2DPControl, EU2FU, EU2Ram, EU2Regs, EU2Utils

EXPORTS EU2Top =

BEGIN OPEN CoreCreate, EU2Top, EU2Utils;

CreateEU2Inner: PUBLIC PROC RETURNS [cellType: CellType] = {

cellType ← Cell[

public: UnionWires[GenPGnEWires[], GenWiresCtrlToPads[], GenWiresDPToPads[]],

onlyInternal: GenWiresCtrlToDP[],

instances: LIST [

Instance[CreateEU2Control[]],

Instance[CreateEU2DataPath[]] ]

];

};

CreateEU2Control: PUBLIC PROC RETURNS [cellType: CellType] = {

SubWire: PROC [public: Wire, sub: ROPE, wireName: WR, start, size: NAT] RETURNS [Wire] ~ {

RETURN[

CoreOps.SetShortWireName[Range[FindWireInWire[public, wireName], start, size], sub]]};

public : Wire ← UnionWires[GenPGnEWires[], GenWiresCtrlToPads[], GenWiresCtrlToDP[]];

onlyInternal: Wire ← Wires[

SubWire[public, "aAdrH", "ramAdr", 0, sizeAdrH],

SubWire[public, "bAdrH", "ramAdr", 8, sizeAdrH],

SubWire[public, "cAdrH", "ramAdr", 16, sizeAdrH],

SubWire[public, "aAdrL", "ramAdr", 0+sizeAdrH, sizeAdrL],

SubWire[public, "bAdrL", "ramAdr", 8+sizeAdrH, sizeAdrL],

SubWire[public, "cAdrL", "ramAdr", 8+sizeAdrH, sizeAdrL]];

cellType ← Cell[

public: public,

onlyInternal: onlyInternal,

instances: LIST[

Instance[EU2RamControl.CreateRamControl[]],

Instance[EU2DPControl.CreateBottomControl[]]]

];

};

CreateEU2DataPath: PUBLIC PROC RETURNS [cellType: CellType] = {

cellType ← Cell[

public: UnionWires[

GenPGnEWires[], -- we probably don't need the clocks

GenWiresDPToPads[], GenWiresCtrlToDP[]],

onlyInternal: Wires[ -- internal busses

Seq["aBus", wordSize], Seq["bBus", wordSize],

Seq["olBus", wordSize], Seq["orBus", wordSize],

Seq["fBus", wordSize], Seq["rBus", wordSize],

Seq["s1Bus", wordSize], Seq["s2Bus", wordSize], Seq["s3Bus", wordSize],

Seq["aluBus", wordSize], Seq["fuBus", wordSize], Seq["tBus", wordSize]],

instances: LIST [

Instance[EU2Ram.CreateEU2Ram[], ["nPrech", "nPhB"]],

Instance[ -- ramAdr

EU2Regs.CreateRegWithMux[inputs: LIST["kBus"], output: "ramAdr"],

["sel", "PhB"], ["dRead", "dReadRamAdr"]],

Instance[ -- aluLeft

EU2Regs.CreateRegWithMux[inputs: LIST["cBus", "rBus", "aBus"], output: "olBus"],

["sel", "selLeftSrc"], ["dRead", "dReadLeft"]],

Instance[ -- aluRight

EU2Regs.CreateRegWithMux[

inputs: LIST["cBus", "rBus", "bBus", "kBus", "fBus"], output: "orBus"],

["sel", "selRightSrc"], ["dRead", "dReadRight"]],

Instance[ -- result2BA

EU2Regs.CreateRegWithMux[inputs: LIST["aluBus", "fuBus"], output: "rBus"],

["sel", "selRes2BASrc"], ["dRead", "dReadRes2BA"]],

Instance[ -- result3AB

EU2Regs.CreateRegWithMux[inputs: LIST["rBus"], output: "tBus"],

["sel", "selRes3ABSrc"], ["dRead", "dReadRes3AB"]],

Instance[ -- cBusResult3BA

EU2Regs.CreateRegWithMux[inputs: LIST["tBus", "dBus"], output: "cBus"],

["sel", "selRes3BASrc"], ["dRead", "dReadRes3BA"]],

Instance[ -- store2AB

EU2Regs.CreateRegWithMux[inputs: LIST["cBus", "rBus", "bBus"], output: "s1Bus"],

["sel", "selSt2ASrc"], ["dRead", "dReadSt2A"]],

Instance[ -- store2BA

EU2Regs.CreateRegWithMux[inputs: LIST["s1Bus"], output: "s2Bus"],

["sel", "selSt2BASrc"], ["dRead", "dReadSt2BA"]],

Instance[ -- store3AB

EU2Regs.CreateRegWithMux[inputs: LIST["cBus", "s2Bus"], output: "s3Bus"],

["sel", "selSt3ABSrc"], ["dRead", "dReadSt3AB"]],

Instance[ -- field

EU2Regs.CreateRegWithMux[inputs: LIST["cBus"], output: "fBus"],

["sel", "selFieldSrc"], ["dRead", "dReadField"]],

Instance[ -- pDriver

EU2Regs.CreatePDriver[],

["address", "rBus"], ["data", "s3Bus"], ["out", "adBus"], ["selAd", "selPBusAd"], ["selData", "selPBusData"], ],

Instance[EU2FU.CreateFieldUnit[], ["left", "olBus"], ["right", "s1Bus"], ["fuOut", "fuBus"]],

Instance[EU2ALU.CreateALU[], ["left", "olBus"], ["right", "orBus"], ["aluOut", "aluBus"]]

]

];

};

END.