<> <> <> <> DIRECTORY CoreCreate, EU2DP, EU2LeafUtils, EU2Utils, Rosemary, Ports; EU2DPImpl: CEDAR PROGRAM IMPORTS CoreCreate, EU2LeafUtils, EU2Utils, Rosemary, Ports EXPORTS EU2DP = BEGIN OPEN CoreCreate, EU2DP, EU2Utils; public: Wire _ Union[ GenPGnEWires[], -- NO clocks GenWiresDPToPads[], GenWiresForRouter[]]; <<-- PGE>> Vdd: PUBLIC NAT _ PortIndex[public, "Vdd"]; Gnd: PUBLIC NAT _ PortIndex[public, "Gnd"]; <<-- from and to pad frame>> fromIFU: PUBLIC NAT _ PortIndex[public, "fromIFU"]; toIFU: PUBLIC NAT _ PortIndex[public, "toIFU"]; toPBus: PUBLIC NAT _ PortIndex[public, "toPBus"]; fromPBus: PUBLIC NAT _ PortIndex[public, "fromPBus"]; <<-- to RAM control>> ramAdr: PUBLIC NAT _ PortIndex[public, "ramAdr"]; <<-- from RAM control to RAM>> selA: PUBLIC NAT _ PortIndex[public, "selA"]; selB: PUBLIC NAT _ PortIndex[public, "selB"]; selC: PUBLIC NAT _ PortIndex[public, "selC"]; selALow: PUBLIC NAT _ PortIndex[public, "selALow"]; selBLow: PUBLIC NAT _ PortIndex[public, "selBLow"]; selCLow: PUBLIC NAT _ PortIndex[public, "selCLow"]; dRamRead: PUBLIC NAT _ PortIndex[public, "dRamRead"]; <<-- to control>> leftSrc: PUBLIC NAT _ PortIndex[public, "leftSrc"]; rightSrc: PUBLIC NAT _ PortIndex[public, "rightSrc"]; st2ASrc: PUBLIC NAT _ PortIndex[public, "st2ASrc"]; loadField: PUBLIC NAT _ PortIndex[public, "loadField"]; zero: PUBLIC NAT _ PortIndex[public, "zero"]; carryOut: PUBLIC NAT _ PortIndex[public, "carryOut"]; res: PUBLIC NAT _ PortIndex[public, "res"]; opL: PUBLIC NAT _ PortIndex[public, "opL"]; opR: PUBLIC NAT _ PortIndex[public, "opR"]; fd: PUBLIC NAT _ PortIndex[public, "fd"]; insertFd: PUBLIC NAT _ PortIndex[public[fd], "insertFd"]; maskFd: PUBLIC NAT _ PortIndex[public[fd], "maskFd"]; shiftFd: PUBLIC NAT _ PortIndex[public[fd], "shiftFd"]; <<-- from control>> pipeRegsSel: PUBLIC NAT _ PortIndex[public, "pipeRegsSel"]; dRead: PUBLIC NAT _ PortIndex[public[pipeRegsSel][0], "dRead"]; sel: PUBLIC NAT _ PortIndex[public[pipeRegsSel][0], "sel"]; carryIn: PUBLIC NAT _ PortIndex[public, "carryIn"]; op: PUBLIC NAT _ PortIndex[public, "op"]; insert: PUBLIC NAT _ PortIndex[public, "insert"]; mask: PUBLIC NAT _ PortIndex[public, "mask"]; shift: PUBLIC NAT _ PortIndex[public, "shift"]; sh: PUBLIC NAT _ PortIndex[public, "sh"]; CreateEU2DataPath: PUBLIC PROC RETURNS [cellType: CellType] = { cellType _ EU2LeafUtils.Extract["EU2DataPath.sch"]; [] _ Rosemary.SetFixedWire[cellType.public[Vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[Gnd], L]; [] _ Ports.InitPort[cellType.public[fromIFU], lc, none]; [] _ Ports.InitPort[cellType.public[toIFU], lc, drive]; [] _ Ports.InitPort[cellType.public[toPBus], lc, drive]; [] _ Ports.InitPort[cellType.public[fromPBus], lc, none]; FOR i: NAT IN [a..c] DO [] _ Ports.InitPort[cellType.public[ramAdr][i][hi], c, drive]; [] _ Ports.InitPort[cellType.public[ramAdr][i][low], c, drive]; ENDLOOP; InitLeafPorts[cellType.public[selA], none]; InitLeafPorts[cellType.public[selB], none]; InitLeafPorts[cellType.public[selC], none]; InitLeafPorts[cellType.public[selALow], none]; InitLeafPorts[cellType.public[selBLow], none]; InitLeafPorts[cellType.public[selCLow], none]; [] _ Ports.InitPort[cellType.public[leftSrc], c, drive]; [] _ Ports.InitPort[cellType.public[rightSrc], c, drive]; [] _ Ports.InitPort[cellType.public[st2ASrc], c, drive]; [] _ Ports.InitPort[cellType.public[loadField], b, drive]; [] _ Ports.InitPort[cellType.public[zero], b, drive]; [] _ Ports.InitPort[cellType.public[carryOut], b, drive]; [] _ Ports.InitPort[cellType.public[res], c, drive]; [] _ Ports.InitPort[cellType.public[opL], c, drive]; [] _ Ports.InitPort[cellType.public[opR], c, drive]; [] _ Ports.InitPort[cellType.public[fd], c, drive]; -- fix it!!! [] _ Rosemary.BindCellType[cellType: cellType, roseClassName: EU2DPClass]; }; EU2DPClass: ROPE = Rosemary.Register[roseClassName: "EU2DP", evalSimple: EU2DPSimple]; EU2DPSimple: Rosemary.EvalProc = {}; END. << TO DO>> EU2DPSimple: Rosemary.EvalProc = { <> <<{OPEN state;>> <> <> <> <> <> <<{IF found THEN ERROR; -- and not two select lines are high>> <> <> <> <> <<};>> <<>> <> <> <<>> <<-- Compute peudo-states first>> <<-- read the RAM>> <> <> <> <> <<-- read input ports>> <> <> <<-- alu computation>> <> <> <> <> < [simRegs[aluOut], p[ccIn][c32].b] _ >> <> < simRegs[aluOut] _ WordAnd[l, r]; >> < simRegs[aluOut] _ WordOr[l, r]; >> < simRegs[aluOut] _ WordXor[l, r]; >> < ERROR;>> <<-- fu computation>> <> <<>> <<-- Update the States>> <<-- ram: always write>> <> <> <<-- pipeline registers>> <> <<-- Drive output ports to control>> <<-- drive ramAdr, leftSrc, rightSrc, st2ASrc and loadField>> <<[aR, bR, cR, p[loadField].b, p[leftSrc].c, p[rightSrc].c, p[st2ASrc].c] >> <<_ ExplodeKReg[simRegs[kReg]];>> <> <> <> <> <> <> <<-- drive ccIn>> <> <> <> <> <<>> <<-- Drive output ports to pads>> <> <> }};