[Indigo]<Dragon>EU2>EU2DPImpl.mesa!10

EU2DPImpl.mesa

Louis Monier March 18, 1986 2:02:59 am PST

Bertrand Serlet March 31, 1986 2:25:40 pm PST

DIRECTORY CoreCreate, EU2DP, EU2LeafUtils, EU2Utils, Rosemary, Ports;

EU2DPImpl: CEDAR PROGRAM

IMPORTS CoreCreate, EU2LeafUtils, EU2Utils, Rosemary, Ports

EXPORTS EU2DP =

BEGIN OPEN CoreCreate, EU2DP, EU2Utils;

public: Wire ← Union[

GenPGnEWires[], -- NO clocks

GenWiresDPToPads[],

GenWiresForRouter[]];

-- PGE

Vdd: PUBLIC NAT ← PortIndex[public, "Vdd"];

Gnd: PUBLIC NAT ← PortIndex[public, "Gnd"];

-- from and to pad frame

fromIFU: PUBLIC NAT ← PortIndex[public, "fromIFU"];

toIFU: PUBLIC NAT ← PortIndex[public, "toIFU"];

toPBus: PUBLIC NAT ← PortIndex[public, "toPBus"];

fromPBus: PUBLIC NAT ← PortIndex[public, "fromPBus"];

-- to RAM control

ramAdr: PUBLIC NAT ← PortIndex[public, "ramAdr"];

-- from RAM control to RAM

selA: PUBLIC NAT ← PortIndex[public, "selA"];

selB: PUBLIC NAT ← PortIndex[public, "selB"];

selC: PUBLIC NAT ← PortIndex[public, "selC"];

selALow: PUBLIC NAT ← PortIndex[public, "selALow"];

selBLow: PUBLIC NAT ← PortIndex[public, "selBLow"];

selCLow: PUBLIC NAT ← PortIndex[public, "selCLow"];

dRamRead: PUBLIC NAT ← PortIndex[public, "dRamRead"];

-- to control

leftSrc: PUBLIC NAT ← PortIndex[public, "leftSrc"];

rightSrc: PUBLIC NAT ← PortIndex[public, "rightSrc"];

st2ASrc: PUBLIC NAT ← PortIndex[public, "st2ASrc"];

loadField: PUBLIC NAT ← PortIndex[public, "loadField"];

zero: PUBLIC NAT ← PortIndex[public, "zero"];

carryOut: PUBLIC NAT ← PortIndex[public, "carryOut"];

res: PUBLIC NAT ← PortIndex[public, "res"];

opL: PUBLIC NAT ← PortIndex[public, "opL"];

opR: PUBLIC NAT ← PortIndex[public, "opR"];

fd: PUBLIC NAT ← PortIndex[public, "fd"];

insertFd: PUBLIC NAT ← PortIndex[public[fd], "insertFd"];

maskFd: PUBLIC NAT ← PortIndex[public[fd], "maskFd"];

shiftFd: PUBLIC NAT ← PortIndex[public[fd], "shiftFd"];

-- from control

pipeRegsSel: PUBLIC NAT ← PortIndex[public, "pipeRegsSel"];

dRead: PUBLIC NAT ← PortIndex[public[pipeRegsSel][0], "dRead"];

sel: PUBLIC NAT ← PortIndex[public[pipeRegsSel][0], "sel"];

carryIn: PUBLIC NAT ← PortIndex[public, "carryIn"];

op: PUBLIC NAT ← PortIndex[public, "op"];

insert: PUBLIC NAT ← PortIndex[public, "insert"];

mask: PUBLIC NAT ← PortIndex[public, "mask"];

shift: PUBLIC NAT ← PortIndex[public, "shift"];

sh: PUBLIC NAT ← PortIndex[public, "sh"];

CreateEU2DataPath: PUBLIC PROC RETURNS [cellType: CellType] = {

cellType ← EU2LeafUtils.Extract["EU2DataPath.sch"];

[] ← Rosemary.SetFixedWire[cellType.public[Vdd], H];

[] ← Rosemary.SetFixedWire[cellType.public[Gnd], L];

[] ← Ports.InitPort[cellType.public[fromIFU], lc, none];

[] ← Ports.InitPort[cellType.public[toIFU], lc, drive];

[] ← Ports.InitPort[cellType.public[toPBus], lc, drive];

[] ← Ports.InitPort[cellType.public[fromPBus], lc, none];

FOR i: NAT IN [a..c] DO

[] ← Ports.InitPort[cellType.public[ramAdr][i][hi], c, drive];

[] ← Ports.InitPort[cellType.public[ramAdr][i][low], c, drive];

ENDLOOP;

InitLeafPorts[cellType.public[selA], none];

InitLeafPorts[cellType.public[selB], none];

InitLeafPorts[cellType.public[selC], none];

InitLeafPorts[cellType.public[selALow], none];

InitLeafPorts[cellType.public[selBLow], none];

InitLeafPorts[cellType.public[selCLow], none];

[] ← Ports.InitPort[cellType.public[leftSrc], c, drive];

[] ← Ports.InitPort[cellType.public[rightSrc], c, drive];

[] ← Ports.InitPort[cellType.public[st2ASrc], c, drive];

[] ← Ports.InitPort[cellType.public[loadField], b, drive];

[] ← Ports.InitPort[cellType.public[zero], b, drive];

[] ← Ports.InitPort[cellType.public[carryOut], b, drive];

[] ← Ports.InitPort[cellType.public[res], c, drive];

[] ← Ports.InitPort[cellType.public[opL], c, drive];

[] ← Ports.InitPort[cellType.public[opR], c, drive];

[] ← Ports.InitPort[cellType.public[fd], c, drive]; -- fix it!!!

[] ← Rosemary.BindCellType[cellType: cellType, roseClassName: EU2DPClass];

};

EU2DPClass: ROPE = Rosemary.Register[roseClassName: "EU2DP", evalSimple: EU2DPSimple];

EU2DPSimple: Rosemary.EvalProc = {};

END.

TO DO

EU2DPSimple: Rosemary.EvalProc = {

state: EU2DPState ← NARROW[stateAny];

{OPEN state;

SetReg: PROC [reg: PipeRange] ~ {

source: SourceRange;

found: BOOL ← FALSE;

FOR i: NAT IN [0..sources[reg].sizeSel) DO

IF p[pipeRegsSel][reg][sel][i].b THEN -- if a select line is up

{IF found THEN ERROR; -- and not two select lines are high

source ← sources[reg].inputs[i];

simRegs[reg] ← simRegs[source]; -- then update the value

found ← TRUE};

ENDLOOP;

};

aAdr, bAdr, cAdr, aR, bR, cR: NAT;

l, r: CARD;

-- Compute peudo-states first

-- read the RAM

aAdr ← p[selA].c*4+p[selALow].c;

bAdr ← p[selB].c*4+p[selBLow].c;

simRegs[ramA] ← ram[aAdr];

simRegs[ramB] ← ram[bAdr];

-- read input ports

simRegs[ifuIn] ← p[fromIFU].lc; -- maybe an immediate operand from the IFU

simRegs[pIn] ← p[toPBus].lc; -- data back from the Cache, or junk

-- alu computation

l ← simRegs[left];

r ← simRegs[right];

IF p[aluCtrl][invB].b THEN r ← WordNot[r];

SELECT TRUE FROM

p[aluCtrl][add].b => [simRegs[aluOut], p[ccIn][c32].b] ←

DoubleADD[l, r, p[aluCtrl][carryIn].b];

p[aluCtrl][and].b => simRegs[aluOut] ← WordAnd[l, r];

p[aluCtrl][or].b => simRegs[aluOut] ← WordOr[l, r];

p[aluCtrl][xor].b => simRegs[aluOut] ← WordXor[l, r];

ENDCASE => ERROR;

-- fu computation

simRegs[fuOut] ← FieldOp[simRegs[left], simRegs[st2A], simRegs[right]];

-- Update the States

-- ram: always write

cAdr ← p[selC].c*4+p[selCLow].c;

IF cAdr IN [stackAdr .. bogusAdr] THEN ram[cAdr] ← simRegs[cBus];

-- pipeline registers

FOR reg: PipeRange IN PipeRange DO SetReg[reg] ENDLOOP;

-- Drive output ports to control

-- drive ramAdr, leftSrc, rightSrc, st2ASrc and loadField

[aR, bR, cR, p[loadField].b, p[leftSrc].c, p[rightSrc].c, p[st2ASrc].c]

← ExplodeKReg[simRegs[kReg]];

p[ramAdr][a][hi].c ← aR/4;

p[ramAdr][a][low].c ← aR MOD 4;

p[ramAdr][b][hi].c ← bR/4;

p[ramAdr][b][low].c ← bR MOD 4;

p[ramAdr][c][hi].c ← cR/4;

p[ramAdr][c][low].c ← cR MOD 4;

-- drive ccIn

p[ccIn][zero].b ← simRegs[r2B]=0;

p[ccIn][res].c ← simRegs[r2B]/4000000000B; -- probably wrong!!!

p[ccIn][opL].c ← simRegs[left]/4000000000B;

p[ccIn][opR].c ← simRegs[right]/4000000000B;

-- Drive output ports to pads

p[toIFU].lc ← simRegs[cBus]; -- cBus, ev. for IFU

p[toPBus].lc ← simRegs[pDriver]; -- adr or data for Cache

}};