<> <> <> DIRECTORY Boole, BooleCore, CoreCreate, EU2DPControl, EU2LeafUtils, EU2Utils, Ports, Rosemary; EU2DPControlImpl: CEDAR PROGRAM IMPORTS Boole, BooleCore, CoreCreate, EU2LeafUtils, EU2Utils EXPORTS EU2DPControl = BEGIN OPEN Boole, BooleCore, CoreCreate, EU2DPControl, EU2Utils; ExprProc: TYPE ~ PROC [i: NAT] RETURNS [Expression]; AppendInput: PROC [name: ROPE, public: Wire, inputD: Inputs] RETURNS [ins: Inputs]~ { wire: Wire _ FindWire[public, name]; inv: CellType _ EU2LeafUtils.AlpsExtract["InputDriver.sch"]; IF wire.size=0 THEN RETURN [CONS[[input: wire, driver: inv], inputD]]; ins _ inputD; FOR i: INT IN [0..wire.size) DO ins _ CONS[[input: Index[wire, i], driver: inv], ins]; ENDLOOP; }; AppendOutput: PROC [wire: WR, expr: Expression, clock: ROPE, outputDrivers: Outputs] RETURNS [Outputs] ~ { out: CellType _ EU2LeafUtils.AlpsExtract["ClockedOutputDriver.sch"]; RETURN [CONS[ [driver: out, pas: LIST[["Clock", clock]], output: wire, expr: expr], outputDrivers]]; }; <<-- Creates the control for the bottom of the Datapath, i.e. everything but the ram and the KBus pads>> CreateDPControl: PUBLIC PROC RETURNS [cellType: CellType] = { MakeSelExpr: PROC [reg: PipeRange, exprProc: ExprProc, clock: ROPE] ~ { FOR i: INT IN [0..sources[reg].sizeSel) DO outputDrivers _ AppendOutput[ wire: Index[sources[reg].nameSel, i], expr: exprProc[i], clock: clock, outputDrivers: outputDrivers]; ENDLOOP; }; inputDrivers: Inputs _ NIL; outputDrivers: Outputs _ NIL; public: Wire _ Union[ -- beware of the order! Wires["hold"], -- a hack for now!!! GenPGnEWires[], GenClockWires[], GenWiresCtrlToPads[], GenWiresPadsToCtrl[], GenWiresDBus[], GenWiresCtrlToRegs[], GenWiresCtrlToALU[], GenWiresCtrlToFU[], GenWiresDPToCtrl[]]; <<-- composite wires to be interpreted as numbers>> leftSrc: Wire _ FindWire[public, "leftSrc"]; rightSrc: Wire _ FindWire[public, "rightSrc"]; st2ASrc: Wire _ FindWire[public, "st2ASrc"]; aluOp: Wire _ FindWire[public, "aluOp"]; fd: Wire _ FindWire[public, "fd"]; insertFd: Wire _ FindWire[fd, "insertFd"]; maskFd: Wire _ FindWire[fd, "maskFd"]; shiftFd: Wire _ FindWire[fd, "shiftFd"]; <<-- expressions on one bit>> reject: Expression _ WireVar[public, "reject"]; -- latched on PhB, simple driver!!! nReject: Expression _ Not[reject]; nHold: Expression _ Not[WireVar[public, "hold"]]; <> st3AisC: Expression _ WireVar[public, "st3AisC"]; fetch: Expression _ WireVar[public, "res3BisP"]; store: Expression _ WireVar[public, "writePBus"]; <<>> <<-- PhA latches>> LeftExpr: ExprProc = {RETURN[And[nReject, nHold, EqualInt[public, leftSrc, i]]]}; -- selLeftSrc[i] _ PhA . (leftSrc=i) . ~reject . ~hold RightExpr: ExprProc = {RETURN[And[nReject, nHold, EqualInt[public, rightSrc, i]]]}; <<-- selRightSrc[i] _ PhA . (rightSrc=i) . ~reject . ~hold>> St2AExpr: ExprProc = {RETURN[And[nReject, nHold, EqualInt[public, st2ASrc, i]]]}; <<-- selSt2ASrc[i] _ PhA . (st2ASrc=i) . ~reject . ~hold>> <> <<-- selFieldSrc _ PhA . loadField . ~reject . ~hold>> R3AExpr: ExprProc = {RETURN[And[nReject, nHold]]}; <<-- selRes3ABSrc _ PhA . ~reject . ~hold>> St3AExpr: ExprProc = {RETURN[ SELECT i FROM 0 => And[nReject, nHold, Not[st3AisC]], 1 => And[nReject, nHold, st3AisC], ENDCASE => ERROR]}; <<-- selSt3ABSrc[st2B] _ PhA . ~st3AisC . ~reject . ~hold>> <<-- selSt3ABSrc[cBus] _ PhA . st3AisC . ~reject . ~hold>> <<-- PhB latches>> KRegExpr: ExprProc = {RETURN[nHold]}; <<-- selKRegAdr _ PhB . ~hold>> R2BExpr: ExprProc = {RETURN[ SELECT i FROM 0 => And[nHold, Nor[ -- aluOut EqualInt[public, aluOp, FOP], -- neither FOP EqualInt[public, aluOp, BndChk]]], -- nor BndChk 1 => And[nHold, EqualInt[public, aluOp, FOP]], -- fuOut 2 => And[nHold, EqualInt[public, aluOp, BndChk]], -- left ENDCASE => ERROR]}; <<-- selRes2BASrc[aluOut] _ PhB . ~hold . (aluOp=FOP)>> <<-- selRes2BASrc[fuOut] _ PhB . ~hold . (aluOp#FOP)>> <<-- selRes2BASrc[left] _ PhB . ~hold . (aluOp=BndChk)>> St2BExpr: ExprProc = {RETURN[nHold]}; <<-- selSt2BASrc _ PhB . ~hold>> R3BExpr: ExprProc = {RETURN[nHold]}; <<-- selRes3BASrc[tBus] _ PhB . ~hold>> DataInExpr: ExprProc = {RETURN[nHold]}; <<-- selDataInSrc _ PhB . ~hold>> <<-- Special guys>> <> <> <<0 => nHold, -- st3A>> <<1 => nHold, -- r2B>> < ERROR]};>> <<-- selPDriverSrc[st3A] _ PhB . ~hold>> <<-- selPDriverSrc[r2B] _ PhA . ~hold (reject???)>> CBusExpr: ExprProc = {RETURN[ -- use the non-latched reject and a simple driver, no clock!!! SELECT i FROM 0 => Nand[nReject, store, fetch], -- r3B 1 => And[nReject, nHold, fetch], -- dataIn ENDCASE => ERROR]}; <<-- selCBusSrc[r3B] _ PhA . (reject + ~fetch + ~store)>> <<-- selCBusSrc[dataIn] _ PhA . ~reject . ~hold . fetch>> <<>> <<-- Field Unit>> InsertExpr: ExprProc = {RETURN[And[nHold, WireVar[public, "insertFd"]]]}; <<-- insert _ ~hold . insertFd>> MaskExpr: ExprProc = {RETURN[ And[nHold, WireVar[public, Index["maskFd", i]]]]}; <<-- mask[i] _ ~hold . maskFd[i]>> ShiftExpr: ExprProc = {RETURN[ And[nHold, WireVar[public, Index["shiftFd", i]]]]}; <<-- shift[i] _ ~hold . shiftFd[i]>> ShExpr: ExprProc = {RETURN[ And[nHold, EqualInt[public, shiftFd, i]]]}; <<-- mask[i] _ ~hold . (shiftFd=i)>> <<>> <<-- ALU>> CarryInExpr: ExprProc = {RETURN[true]}; <<-- carryIn _ a big mess!!!>> OpExpr: ExprProc = {RETURN[true]}; <<-- op[i] _ a big mess!!!>> <<>> <<-- Carry and condition>> <<>> <<>> <<-- Data path in order>> MakeSelExpr[kReg, KRegExpr, "phB"]; MakeSelExpr[right, RightExpr, "phA"]; <> MakeSelExpr[left, LeftExpr, "phA"]; MakeSelExpr[st2A, St2AExpr, "phA"]; <<-- aluCtrl>> MakeSelExpr[r2B, R2BExpr, "phB"]; <<-- fuCtrl>> MakeSelExpr[st2B, St2BExpr, "phB"]; MakeSelExpr[st3A, St3AExpr, "phA"]; <> MakeSelExpr[r3A, R3AExpr, "phA"]; MakeSelExpr[r3B, R3BExpr, "phB"]; MakeSelExpr[cBus, CBusExpr, "none"]; MakeSelExpr[dataIn, DataInExpr, "phB"]; <<-- To pad frame>> <> <> <> <<>> <<-- Input Drivers for the signals coming from the Data Path>> inputDrivers _ AppendInput["leftSrc", public, inputDrivers]; -- 2 inputDrivers _ AppendInput["rightSrc", public, inputDrivers]; -- 3 inputDrivers _ AppendInput["st2ASrc", public, inputDrivers]; -- 2 inputDrivers _ AppendInput["zero", public, inputDrivers]; -- 1 inputDrivers _ AppendInput["carryOut", public, inputDrivers]; -- 1 inputDrivers _ AppendInput["res", public, inputDrivers]; -- 8 inputDrivers _ AppendInput["opL", public, inputDrivers]; -- 3 inputDrivers _ AppendInput["opR", public, inputDrivers]; -- 3 inputDrivers _ AppendInput["fd", public, inputDrivers]; -- 13 <<-- Input Drivers for the (few) signals coming straight from the pads>> inputDrivers _ AppendInput["st3AisC", public, inputDrivers]; -- 1 inputDrivers _ AppendInput["res3BisP", public, inputDrivers]; -- 1 inputDrivers _ AppendInput["writePBus", public, inputDrivers]; -- 1 inputDrivers _ AppendInput["reject", public, inputDrivers]; -- 1 inputDrivers _ AppendInput["aluOp", public, inputDrivers]; -- 4 inputDrivers _ AppendInput["condSel", public, inputDrivers]; -- 4 <<>> <<-- Generate the block Alps>> cellType _ NIL; <> <> <> <> <> <<];>> }; END. <<-- Inputs to the Alps blocks>> leftSrc, rightSrc, st2ASrc, loadField, zero, -- form DP st3AisC, res3BisP, writePBus, reject, aluOp, condSel -- form pads <<-- PhA latches>> -- aluLeft selLeftSrc[i] _ ClockedDriver[PhA, (leftSrc=i) AND ~reject] dReadLeft _ ClockedDriver[] -- aluRight selRightSrc[i] _ ClockedDriver[PhA, (rightSrc=i) AND ~reject] dReadRight _ ClockedDriver[] -- store2AB selSt2ASrc[i] _ ClockedDriver[PhA, (st2ASrc=i) AND ~reject] dReadSt2A _ ClockedDriver[] -- result3AB selRes3ABSrc _ ClockedDriver[PhA, ~reject] dReadRes3AB _ ClockedDriver[] -- store3AB selSt3ABSrc[cBus] _ ClockedDriver[PhA, st3AisC AND ~reject] selSt3ABSrc[s2Bus] _ ClockedDriver[PhA, ~st3AisC AND ~reject] dReadSt3AB _ ClockedDriver[] -- field selFieldSrc _ ClockedDriver[PhA, loadField AND ~reject] dReadField _ ClockedDriver[] <<>> <<-- PhB latches>> <<>> -- ramAdr selRamAdr _ ClockedDriver[PhB, true] -- result2BA selRes2BASrc[aluBus] _ ClockedDriver[PhB, ~(aluOp=FOP)] selRes2BASrc[fuBus] _ ClockedDriver[PhB, (aluOp=FOP)] dReadRes2BA _ ClockedDriver[] -- cBusResult3BA selRes3BASrc[tBus] _ ClockedDriver[PhB, ] selRes3BASrc[dBus] _ ClockedDriver[PhB, ] dReadRes2BA _ ClockedDriver[] -- store2BA selSt2BASrc _ ClockedDriver[PhB, true] <<-- PBus driver>> 1. PhA AND ~reject: drive PBus (send address to cache from adBus) 2. PhA AND reject: don't drive PBus (cache has latched the address) 3. PhB AND EUWriteToPBus3AB: drive PBus (send data for store from dBus, even if there is a reject) 4. PhB AND ~EUWriteToPBus3AB AND reject: nothing on PBus (copy faulty address to res3B) 5. PhB AND ~EUWriteToPBus3AB AND ~reject AND ~EURes3BisPBus3AB: nothing on PBus (copy faulty address to res3B) 6. PhB AND ~EUWriteToPBus3AB AND ~reject AND EURes3BisPBus3AB: read on PBus (get data from cache into res3B) Combining 4 and 5, and using a OR (~a AND b) = a OR b: 4.5. PhB AND ~EUWriteToPBus3AB AND (reject OR ~EURes3BisPBus3AB): nothing on PBus (copy faulty address to res3B)