EU2.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Louis Monier June 2, 1986 3:52:58 pm PDT
McCreight, April 10, 1986 12:13:37 pm PST
Barth, April 19, 1986 5:23:49 pm PST
Bertrand Serlet June 7, 1986 7:10:28 pm PDT
DIRECTORY Core, Dragon, DragOpsCross, EU2Arith, EU2Utils, Ports, Rosemary;
EU2: CEDAR DEFINITIONS = BEGIN OPEN EU2Arith;
Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, VRef,
DPRejectB, DPData, -- 32 bits
KBus, --
32 bits
-- Phase-multiplexed on KBus
aAdr [0..7]
bAdr [8..15]
cAdr [16..23]
EUSt3AisCBus2BA [24]
EUAluLeftSrc1BA [25..26]
EUAluRightSrc1BA [27..29]
EUStore2ASrc1BA [30..31]
EURes3BisPBus3AB, EUWriteToPBus3AB,
EUAluOp2AB, -- 4 bits Dragon.ALUOps
EUCondSel2AB, -- 4 bits Dragon.CondSelects
EUCondition2B,
DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT;
NoteRegStoreProc: TYPE = PROC [ data: REF ANY, reg: [0..256), value: CARD ];
EUTypeData:
TYPE =
RECORD [
data: REF ANY,
storeNoted: BOOL,
noteStore: NoteRegStoreProc ← NIL
];
nRegs: NAT = 160;
EU2State: TYPE = REF EU2StateRec;
EU2StateRec:
TYPE =
RECORD[
-- kitchen sink
data: REF EUTypeData ← NIL,
-- registers
simRegs: ARRAY EU2Utils.PipeRange OF CARD ← ALL[0],
-- a few bits of state
carryAB, carryBA: BOOL ← FALSE,
conditionBA: BOOL ← FALSE, -- needed during A to update carryAB
rejectBA: BOOL ← FALSE, -- a copy of DPRejectB stable during PhiA
-- register file
ram: SEQUENCE size: NAT OF CARD
size: NAT ← nRegs,
ram: ARRAY [0..nRegs) OF CARD
];
The EU2 register file is organised as follows (Ref DragOpsCross.mesa):
0..127: the stack 128 words
128: euJunk used to specify no write
129: euToKBus send result on K bus to IFU
130: euMAR Memory Address Register
131: euField Field register, an alias of "field"
132..143 constant 12 constant registers
144..159 auxilliary 16 auxilliary registers
Any aAdr larger than euBogus=160 is illegal
Note: ram[132] is the constant zero, implemented by a ROM
CreateEU2: PUBLIC PROC [ typeData: REF EUTypeData ← NIL, fullEU: BOOL ← FALSE ] RETURNS [cellType: Core.CellType];
END.
aluLeft, aluRight, result2BA, result3AB, cBusResult3BA, store2AB, store2BA, store3AB: CARD,
field: CARD, -- a copy of field is kept as RAM[fieldAdr], another copy is in the field unit. Any write is performed to both physical locations, any read is from the most convenient location.
-- carryBA is the output of the adder modified by the opcode of the previous operation and latched if no trap; carryAB is a copy of carryBA if there is no reject or trap.
Remarks:
euJunk could be constant0, since it is a word of ROM.
euToKBus could be an address above 160, and does not need a word in RAM
euField could probably disppear since the register "field" can be read into "right"
We are left with euMAR; if we push more, we can get rid of an entire row in the RAM