AlpsChip.mesa
Copyright © 1985 by Xerox Corporation. All rights reversed.
Bertrand Serlet June 16, 1986 1:13:06 am PDT
DIRECTORY
Boole, BooleCore, BooleCoreImpl, CD, Core, CoreClasses, CoreCreate, CoreProperties, PadFrame, PW, PWCore, Rope, Sisyph;
AlpsChip: CEDAR PROGRAM
IMPORTS Boole, BooleCore, CoreCreate, CoreProperties, PadFrame, PWCore, Sisyph =
BEGIN OPEN Boole, BooleCore, CoreCreate;
design: CD.Design ← BooleCore.cellLibrary;
cx: Sisyph.Context ← BooleCore.cx;
inputDriver: CellType ← AlpsExtract["InputDriver.sch"];
clockedOutputDriver: CellType ← AlpsExtract["ClockedOutputDriver.sch"];
outputDriver: CellType ← AlpsExtract["OutputDriver.sch"];
stateOutputDriver: CellType ← AlpsExtract["StateOutputDriver.sch"];
AlpsExtract: PROC [name: ROPE] RETURNS [cellType: CellType] ~ {
cellType ← Sisyph.ExtractSchematicByName[name: name, cx: cx];
PWCore.SetGet[cellType, design];
};
ConsInput: PROC [public: Wire, wr: WR, inputD: Inputs] RETURNS [ins: Inputs]~ {
ins ← CONS [[input: FindWire[public, wr], driver: inputDriver], inputD];
};
ConsOutput: PROC [wire: WR, expr: Expression, clock: ROPE ← NIL, outputDrivers: Outputs] RETURNS [Outputs] ~ {
out: CellType ← IF clock=NIL THEN outputDriver ELSE clockedOutputDriver;
RETURN [CONS[
[driver: out,
pas: IF clock=NIL THEN LIST[["VRef", "VRef"]]
ELSE LIST[["Clock", clock], ["VRef", "VRef"]],
output: wire, expr: expr],
outputDrivers]];
};
ConsState: PROC [wire: WR, expr: Expression, clock: ROPE, outputDrivers: Outputs] RETURNS [Outputs] ~ {
out: CellType ← stateOutputDriver;
IF clock=NIL THEN ERROR; -- need a clock to latch the state
RETURN [CONS[
[driver: out,
pas: LIST[["Latch", clock], ["VRef", "VRef"]],
output: wire, expr: expr],
outputDrivers]];
};
AlpsCellType: PUBLIC PROC [] RETURNS [ct: CellType] = {
expr: Expression ← true;
expr4: Expression;
public: Wire ← WireList[LIST [
Seq["In", 16],
"Osc1In", "Osc2In", "Osc3In", "SecondAnd4In",
"Osc1", "Osc2", "Osc3", "OscOut",
Seq["And", 9], "And16", "FarAnd4", "Unclocked4", "FirstAnd4", "SecondAnd4",
"Xor2", "Xor3", "Xor4", "State",
"phA", "Gnd", "Vdd", "VRef"]];
inputDrivers: Inputs ← NIL;
outputDrivers: Outputs ← NIL;
In: Wire ← FindWire[public, "In"];
inputDrivers ← ConsInput[public, "Osc1In", inputDrivers];
inputDrivers ← ConsInput[public, "Osc2In", inputDrivers];
inputDrivers ← ConsInput[public, "Osc3In", inputDrivers];
inputDrivers ← ConsInput[public, "SecondAnd4In", inputDrivers];
FOR i: NAT IN [0 .. 16) DO inputDrivers ← ConsInput[public, In[i], inputDrivers] ENDLOOP;
outputDrivers ← ConsOutput["Osc1", Not[WireVar[public, "Osc1In"]], "phA", outputDrivers];
outputDrivers ← ConsOutput["Osc2", Not[WireVar[public, "Osc2In"]], "phA", outputDrivers];
outputDrivers ← ConsOutput["Osc3", Not[WireVar[public, "Osc3In"]], "phA", outputDrivers];
outputDrivers ← ConsOutput["OscOut", WireVar[public, "Osc3In"], "phA", outputDrivers];
FOR i: NAT IN [0 .. 9) DO
outputDrivers ← ConsOutput[Index["And", i], expr, "phA", outputDrivers];
expr ← And[expr, WireVar[public, In[i]]];
IF i=3 THEN expr4 ← expr;
ENDLOOP;
FOR i: NAT IN [9 .. 16) DO expr ← And[expr, WireVar[public, In[i]]] ENDLOOP;
outputDrivers ← ConsOutput["And16", expr, "phA", outputDrivers];
outputDrivers ← ConsOutput["FarAnd4", And[WireVar[public, In[15]], WireVar[public, In[14]], WireVar[public, In[13]], WireVar[public, In[12]]], "phA", outputDrivers];
outputDrivers ← ConsOutput["Unclocked4", expr4, NIL, outputDrivers];
outputDrivers ← ConsOutput["FirstAnd4", expr4, "phA", outputDrivers];
outputDrivers ← ConsOutput["SecondAnd4", WireVar[public, "SecondAnd4In"], "phA", outputDrivers];
outputDrivers ← ConsOutput["Xor2", Xor[WireVar[public, In[1]], WireVar[public, In[0]]], "phA", outputDrivers];
outputDrivers ← ConsOutput["Xor3", Xor[WireVar[public, In[2]], WireVar[public, In[1]], WireVar[public, In[0]]], "phA", outputDrivers];
outputDrivers ← ConsOutput["Xor4", Xor[WireVar[public, In[3]], WireVar[public, In[2]], WireVar[public, In[1]], WireVar[public, In[0]]], "phA", outputDrivers];
outputDrivers ← ConsState["State", expr4, "phA", outputDrivers];
ct ← AlpsCell[
name: "AlpsTest",
public: public,
inputs: inputDrivers,
outputs: outputDrivers,
props: CoreProperties.Props[[$ContactPolyMetal2, NEW [INT ← 8]]]
];
};
CreateWholeChip: PROC [alpsCT: CellType] RETURNS [cellType: CellType] = {
public: Wire ← WireList[LIST[
"PadIn0", "PadIn1", "PadIn2", "PadIn3To15",
"PadOscOut", Seq["PadAnd", 9], "PadAnd16", "PadFarAnd4", "PadUnclocked4", "PadSecondAnd4", "PadXor2", "PadXor3", "PadXor4", "PadState",
"PadPhA", "PadPhAOut", "PadnPhAOut", "PadVdd", "PadGnd", "Gnd", "Vdd", "VRef"]];
onlyInternal: Wire;
pas: LIST OF PA;
iL: CellInstances;
onlyInternal ← WireList[LIST[
"In0", "In1", "In2", "In3To15",
"Osc1", "Osc2", "Osc3", "OscOut",
Seq["And", 9], "And16", "FarAnd4", "Unclocked4", "FirstAnd4", "SecondAnd4",
"Xor2", "Xor3", "Xor4", "State",
"phA", "nPhA"]];
pas ← LIST [
["In", WireList[LIST["In0", "In1", "In2", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15", "In3To15"]]],
["Osc1In", "Osc3"], ["Osc2In", "Osc1"], ["Osc3In", "Osc2"], ["SecondAnd4In", "FirstAnd4"]
];
iL ← LIST [InstanceList[alpsCT, pas]];
iL ← PadFrame.AddPad[iL, "VRef", $Analog, 4];
iL ← PadFrame.AddPad[iL, "PadPhA", $Clk, 5, ["Clock", "phA"], ["nClock", "nPhA"]];
iL ← PadFrame.AddPad[iL, NIL, $Logo, 6];
iL ← PadFrame.AddPad[iL, "PadIn0", $In, 11, ["toChip", "In0"]];
iL ← PadFrame.AddPad[iL, "PadIn1", $In, 12, ["toChip", "In1"]];
iL ← PadFrame.AddPad[iL, "PadIn2", $In, 13, ["toChip", "In2"]];
iL ← PadFrame.AddPad[iL, "PadIn3To15", $In, 14, ["toChip", "In3To15"]];
iL ← PadFrame.AddPad[iL, "PadOscOut", $Out, 15, ["fromChip", "OscOut"]];
iL ← PadFrame.AddPad[iL, "PadAnd16", $Out, 16, ["fromChip", "And16"]];
iL ← PadFrame.AddPad[iL, "PadFarAnd4", $Out, 17, ["fromChip", "FarAnd4"]];
iL ← PadFrame.AddPad[iL, "PadUnclocked4", $Out, 18, ["fromChip", "Unclocked4"]];
iL ← PadFrame.AddPad[iL, "PadSecondAnd4", $Out, 19, ["fromChip", "SecondAnd4"]];
iL ← PadFrame.AddPad[iL, "PadPhAOut", $Out, 20, ["fromChip", "phA"]];
iL ← PadFrame.AddPad[iL, "PadnPhAOut", $Out, 21, ["fromChip", "nPhA"]];
iL ← PadFrame.AddPad[iL, "PadState", $Out, 22, ["fromChip", "State"]];
iL ← PadFrame.AddPad[iL, "Vdd", $Vdd, 27];
iL ← PadFrame.AddPad[iL, "Gnd", $Gnd, 28];
iL ← PadFrame.AddPad[iL, "PadVdd", $PadVdd, 29];
FOR i: NAT IN [0 .. 9) DO
iL ← PadFrame.AddPad[iL, Index["PadAnd", i], $Out, 34+i, ["fromChip", Index["And", i]]];
ENDLOOP;
iL ← PadFrame.AddPad[iL, "PadXor2", $Out, 43, ["fromChip", "Xor2"]];
iL ← PadFrame.AddPad[iL, "PadXor3", $Out, 44, ["fromChip", "Xor3"]];
iL ← PadFrame.AddPad[iL, "PadXor4", $Out, 45, ["fromChip", "Xor4"]];
cellType ← Cell[name: "WholeChip",
public: public,
onlyInternal: onlyInternal,
instances: iL];
PWCore.SetLayout[cellType, $PadFrame, PadFrame.padFrameParamsProp, NEW[PadFrame.PadFrameParametersRec ← [nbPadsX: 13, nbPadsY: 10, horizLayer: "met", vertLayer: "met2"]]];
};
END.
Install PadFrame
Run -a AlpsChip
← &ct ← AlpsChip.AlpsCellType[]
← &ob ← PWCore.Layout[&ct]
← &chipct ← AlpsChip.CreateWholeChip[&ct]
← &ob ← PWCore.Layout[&chipct]
← PW.Draw[&ob]