<> <> CIRCUIT[Lambda _ 1, Temp _ 25] = { Vdd: node; powerSupply: voltage[Vdd, Gnd] = 5.0; ! ThymeBasics.thy ! CMOS2.0u25C.thy <> <<>> PData, DataO, DataI, EnableWr, nEnableWr, DriveLow, PDriveLow, nDriveHigh, NnDriveHigh, nData, nPData, nNData, VVdd, VGnd: node; <> <> Q1: CTran[DataI, VVdd, nDriveHigh | W _ 64]; Q2: CTran[EnableWr, VVdd, nDriveHigh | W _ 64]; Q3: ETran[EnableWr, nDriveHigh, NnDriveHigh | W _ 16]; Q4: ETran[DataI, NnDriveHigh, VGnd | W _ 16]; Q5: CTran[DataI, VVdd, PDriveLow | W _ 64]; Q6: CTran[nEnableWr, PDriveLow, DriveLow | W _ 64]; Q7: ETran[DataI, DriveLow, VGnd | W _ 16]; Q8: ETran[nEnableWr, DriveLow, VGnd | W _ 16]; Q9: CTran[nDriveHigh, VVdd, PData | W _ 600]; Q10: ETran[DriveLow, PData, VGnd | W _ 300]; Q11: CTran[EnableWr, VVdd, nEnableWr | W _ 16]; Q12: ETran[EnableWr, nEnableWr, VGnd | W _ 8]; Q13: CTran[PData, VVdd, nData | W _ 8]; Q14: ETran[PData, nData, VGnd | W _ 64]; Q15: CTran[nData, VVdd, nPData | W _ 64]; Q16: CTran[EnableWr, nPData, DataO | W _ 64]; Q17: ETran[nEnableWr, DataO, nNData | W _ 32]; Q18: ETran[nData, nNData, VGnd | W _ 32]; C1: capacitor[PData, Gnd] = 50pF; ?: RectWave[DataI | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 20ns]; ?: RectWave[EnableWr | period _ 200ns, width _ 100ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 0ns]; <<>> }; PLOT["CrossRAM output buffer", :1ns, -1, 6, PData, DataI, DataO, EnableWr, DriveLow, nDriveHigh--, VVddSupply^:10mA, VGndSupply^:10mA-- ]; RUN[tMax _ 100ns];