IOTstPad.thy
Last Edited by: Monier, June 25, 1985 2:00:16 pm PDT
Last Edited by: Khalil, June 25, 1985 9:36:14 am PDT
CIRCUIT[Lambda ← 1, Temp ← 25] = {
Vdd: node;
powerSupply: voltage[Vdd, Gnd] = 5.0;
! ThymeBasics.thy
! CMOS2.0u25C.thy
Pad Output Buffer
PData, DataO, DataI, EnableWr, nEnableWr, DriveLow, PDriveLow, nDriveHigh, NnDriveHigh, nData, nPData, nNData, VVdd, VGnd: node;
VVddSupply: inductor[Vdd, VVdd] = (32/7)*5.0nH;
VGndSupply: inductor[VGnd, Gnd] = (32/7)*5.0nH;
Q1: CTran[DataI, VVdd, nDriveHigh | W ← 64];
Q2: CTran[EnableWr, VVdd, nDriveHigh | W ← 64];
Q3: ETran[EnableWr, nDriveHigh, NnDriveHigh | W ← 16];
Q4: ETran[DataI, NnDriveHigh, VGnd | W ← 16];
Q5: CTran[DataI, VVdd, PDriveLow | W ← 64];
Q6: CTran[nEnableWr, PDriveLow, DriveLow | W ← 64];
Q7: ETran[DataI, DriveLow, VGnd | W ← 16];
Q8: ETran[nEnableWr, DriveLow, VGnd | W ← 16];
Q9: CTran[nDriveHigh, VVdd, PData | W ← 600];
Q10: ETran[DriveLow, PData, VGnd | W ← 300];
Q11: CTran[EnableWr, VVdd, nEnableWr | W ← 16];
Q12: ETran[EnableWr, nEnableWr, VGnd | W ← 8];
Q13: CTran[PData, VVdd, nData | W ← 8];
Q14: ETran[PData, nData, VGnd | W ← 64];
Q15: CTran[nData, VVdd, nPData | W ← 64];
Q16: CTran[EnableWr, nPData, DataO | W ← 64];
Q17: ETran[nEnableWr, DataO, nNData | W ← 32];
Q18: ETran[nData, nNData, VGnd | W ← 32];
C1: capacitor[PData, Gnd] = 50pF;
?: RectWave[DataI | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 20ns];
?: RectWave[EnableWr | period ← 200ns, width ← 100ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 0ns];
};
PLOT["CrossRAM output buffer", :1ns, -1, 6, PData, DataI, DataO, EnableWr, DriveLow, nDriveHigh--, VVddSupply^:10mA, VGndSupply^:10mA-- ];
RUN[tMax ← 100ns];