<> <> CIRCUIT[Lambda _ 1, Temp _ 25] = { Vdd: node; ! ThymeBasics ! CMOS2.0u25C <<-- Bit Line>> nPrecharge, State, nState, Bit, nBit, Sel: node; powerSupply: voltage[Vdd, Gnd] = 5.0; Inverter: circuit[Gnd, Vdd, Input, Output | sizeN _ 4, sizeP _ 4] = { PU: CTran[Input, Vdd, Output| W_sizeP]; PD: ETran[Input, Gnd, Output| W_sizeN]; }; <<-- RAM cell>> invState: Inverter[Gnd, Vdd, State, nState | sizeN _ 12, sizeP _ 3]; invnState: Inverter[Gnd, Vdd, nState, State | sizeN _ 12, sizeP _ 3]; accState: ETran[Sel, Bit, State | W _ 4]; accnState: ETran[Sel, nBit, nState | W _ 4]; <<-- Precharge of bit lines>> prechB: CTran[nPrecharge, Vdd, Bit | W _ 4]; prechnB: CTran[nPrecharge, Vdd, nBit | W _ 4]; <<-- Capas>> CSel: capacitor[Sel, Gnd] = 1pF; CBit: capacitor[Bit, Gnd] = 1pF; CnBit: capacitor[nBit, Gnd] = 1pF; nprech: RectWave[nPrecharge | OnLevel _ 0V, OffLevel _ 5V, period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns]; sel: RectWave[Sel |period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 50ns]; <<>> }; IC[0, Vdd _ 5.0, State _ 5.0, nState _ 0.0]; PLOT["EURAM", :1ns, -1, 6, Sel, nPrecharge, State, nState, Bit, nBit, powerSupply^:-1.0mA]; RUN[tMax _ 100ns];