-- Bit Line
nPrecharge, State, nState, Bit, nBit, Sel: node;
powerSupply: voltage[Vdd, Gnd] = 5.0;
Inverter: circuit[Gnd, Vdd, Input, Output | sizeN ← 4, sizeP ← 4] = {
PU: CTran[Input, Vdd, Output| W←sizeP];
PD: ETran[Input, Gnd, Output| W←sizeN];
};
-- RAM cell
invState: Inverter[Gnd, Vdd, State, nState | sizeN ← 12, sizeP ← 3];
invnState: Inverter[Gnd, Vdd, nState, State | sizeN ← 12, sizeP ← 3];
accState: ETran[Sel, Bit, State | W ← 4];
accnState: ETran[Sel, nBit, nState | W ← 4];
-- Precharge of bit lines
prechB: CTran[nPrecharge, Vdd, Bit | W ← 4];
prechnB: CTran[nPrecharge, Vdd, nBit | W ← 4];
-- Capas
CSel: capacitor[Sel, Gnd] = 1pF;
CBit: capacitor[Bit, Gnd] = 1pF;
CnBit: capacitor[nBit, Gnd] = 1pF;
nprech: RectWave[nPrecharge | OnLevel ← 0V, OffLevel ← 5V, period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns];
sel: RectWave[Sel |period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 50ns];