DIRECTORY BasicTime, CD, CDCells, CDCreateLabels, CDPinObjects, CMos, Convert, EuControl, EuGen, Graphics, PGA144, PW, PWCmos, PWDescr, Onion, PWPins, Rope; EU: CEDAR PROGRAM IMPORTS BasicTime, CD, CDCells, CDCreateLabels, CDPinObjects, CMos, Convert, EuControl, EuGen, Graphics, PGA144, PW, PWCmos, PWDescr, Onion, PWPins, Rope = BEGIN ROPE: TYPE = Rope.ROPE; l: INT = CD.lambda; padFrameInnerSize: CD.Position = [7600*l, 6000*l]; padNames: LIST OF ROPE = LIST[ "empty19", "EULoadField3BA", "EUAluOp2AB", "EURes3BisPBus3AB", "EUWriteToPBus3AB", "nrejectBA", "PhA", "PhB", "nPhA", "nPhB", "nhold2BA", "DExecute", "DStateAddress", "EPData.enableWrite", "EPData", "kBus.enableWrite", "kBus"]; -- also used to carry: "EUAluLeftSrc1BA", "EUAluRightSrc1BA", "EUStore2ASrc1BA", "EURes3AisCBus2BA", and "EUSt3AisCBus2BA" (8 bits) MakeEU: PW.UserProc = BEGIN MakeVia: PROC [x, y: INT] RETURNS [via: PW.ObPtr] = BEGIN via _ PW.CreateEmptyCell[]; PW.IncludeInCell[design, via, PWCmos.Rect[CMos.met2, [x-4*l, y]], [0, 0]]; PW.IncludeInCell[design, via, PWCmos.Rect[CMos.met, [x-4*l, y]], [4*l, 0]]; PW.IncludeInCell[design, via, PWCmos.Rect[CMos.cut2, [x-10*l, y-2*l]], [5*l, l]]; PW.IncludeInDirectory[design, via, "via"]; END; RightExtension: PROC [design: CD.Design, obj: PW.ObPtr, extensionOutOfIR: INT _ 0] RETURNS [cell: PW.ObPtr] = BEGIN ProcessPinOnEdge: PWPins.AppEnumerator = BEGIN side: PWPins.Side _ PWPins.GetSide[obj, app].side; IF side=PWPins.right THEN { name: ROPE _ CDPinObjects.GetName[app]; SELECT TRUE FROM Rope.Equal[name, "vdd"] => -- just a piece of wire PW.IncludeInCell[design, cell, PWCmos.Rect[CMos.met2, [bridgeWidth, app.ob.size.y]], [iRect.x1, app.location.y-iRect.y1]]; Rope.Equal[name, "gnd"] => -- a via of appropriate size PW.IncludeInCell[design, cell, MakeVia[bridgeWidth, app.ob.size.y], [iRect.x1, app.location.y-iRect.y1]]; ENDCASE => NULL; }; END; bridgeWidth: INT = 14*l; iRect: CD.Rect _ CD.InterestRect[obj]; -- copy interestRect of obj; cell _ PW.CreateEmptyCell[]; CDCells.SetInterestRect[cell, [0, 0, bridgeWidth, iRect.y2-iRect.y1]]; -- set interestRect of cell [] _ PWPins.EnumerateEdgePins[obj, ProcessPinOnEdge]; PW.IncludeInCell[design, cell, PWCmos.Rect[CMos.met2, [extensionOutOfIR, iRect.y2-iRect.y1]], -- hack [bridgeWidth, 0]]; PW.IncludeInCell[design, cell, PWCmos.Rect[CMos.met, [extensionOutOfIR, iRect.y2-iRect.y1]], -- hack [bridgeWidth, 0]]; PW.IncludeInDirectory[design, cell, "rightExtension"]; END; EUIncreasingGen: PROC RETURNS [eu: PW.ObPtr] = BEGIN rightPowerBus: PW.ObPtr; eu _ PW.AbutListY[design, LIST[ EuGen.ResultRegsGen[design], EuGen.ALUGen[design], EuGen.FieldUnitGen[design], EuGen.PipeLineRegsGen[design], EuGen.FDRegsGen[design], EuGen.AdrRegGen[design], EuGen.DrivekBusGen[design], EuGen.BitLinesReadWriteGen[design], EuGen.BitLinesMuxesGen[design], EuGen.RAMGen[design] ]]; rightPowerBus _ RightExtension[design, eu, 200*l]; eu _ PW.AbutX[design, eu, rightPowerBus]; PW.RenameObject[design, eu, "EU"]; END; RenamePadsProc: PWPins.RenameProc = BEGIN newRope _ SELECT TRUE FROM Rope.Match["*.dataIn", oldRope] => Rope.Substr[oldRope, 0, Rope.Size[oldRope]-7], Rope.Match["*.dataOut", oldRope] => Rope.Substr[oldRope, 0, Rope.Size[oldRope]-8], ENDCASE => oldRope; END; PadFrame: PROC RETURNS [frame: PW.ObPtr] = BEGIN padDescr: PWDescr.Descriptor; padDescr _ PWDescr.RopesToDescr[padNames]; PWDescr.SetTypePad[padDescr, "PhA", PGA144.Single[3], $Clock]; PWDescr.SetTypePad[padDescr, "nPhA", PGA144.Single[4], $Clock]; PWDescr.SetTypePad[padDescr, "PhB", PGA144.Single[5], $Clock]; PWDescr.SetTypePad[padDescr, "nPhB", PGA144.Single[6], $Clock]; PWDescr.SetTypePad[padDescr, "EUAluOp2AB", PGA144.Segment[7,5], $In]; PWDescr.SetTypePad[padDescr, "EULoadField3BA", PGA144.Single[12], $In]; PWDescr.SetTypePad[padDescr, "nrejectBA", PGA144.Single[13], $In]; PWDescr.SetTypePad[padDescr, "nhold2BA", PGA144.Single[14], $In]; PWDescr.SetTypePad[padDescr, "EURes3BisPBus3AB", PGA144.Single[15], $In]; PWDescr.SetTypePad[padDescr, "EUWriteToPBus3AB", PGA144.Single[16], $In]; PWDescr.SetTypePad[padDescr, "DExecute", PGA144.Single[17], $In]; PWDescr.SetTypePad[padDescr, "DStateAddress", PGA144.Segment[20,4], $In]; PWDescr.SetTypePad[padDescr, "EPData.enableWrite", PGA144.Single[38], $In]; PWDescr.SetTypePad[padDescr, "EPData", PGA144.Segment[39,32], $IOTst]; PWDescr.SetTypePad[padDescr, "empty19", PGA144.Segment[87,19],$Empty]; PWDescr.SetTypePad[padDescr, "kBus", PGA144.Segment[110,32],$IOTst]; PWDescr.SetTypePad[padDescr, "kBus.enableWrite", PGA144.Single[144], $In]; frame _ PGA144.MakePadFrame[design, padDescr, padFrameInnerSize]; END; MakeLogo: PROC RETURNS [logo: PW.ObPtr] = BEGIN now, name: ROPE; font: Graphics.FontRef; now _ Convert.RopeFromTime[from: BasicTime.Now[], start: years, end: days]; font _ Graphics.MakeFont["TimesRomanD24"]; logo _ CDCreateLabels.CreateTextCell[design, name, font, 4, CMos.met]; END; RenameInnerPins: PROC [design: CD.Design, obj: PW.ObPtr] RETURNS [cell: PW.ObPtr] = BEGIN Rename: PWPins.RenameProc= BEGIN Propagate: PROC [lNames: LIST OF ROPE] = {newRope _ NIL; FOR l: LIST OF ROPE _ lNames, l.rest WHILE l#NIL DO IF Rope.Find[oldRope, l.first]#-1 THEN {newRope _ oldRope; EXIT}; ENDLOOP;}; Propagate[padNames]; END; cell _ PWPins.RenamePins[design, obj, Rename]; END; MakeCompleteEu: PROC RETURNS [eu: PW.ObPtr] = BEGIN inner, outer, copyrightSign, myName: CD.ObPtr; innerPos: CD.Position; layersParams: Onion.LayersParameters _ Onion.defaultLayersParameters; layersParams.wireExtendProc _ Onion.WireExtendPolToMetForPads; EuControl.InitEUControl[design]; inner _ Onion.MakeInner[design, RenameInnerPins[design, EUIncreasingGen[]]]; PW.SetDefaultSource[design, PW.OpenDesign["///Logo.dale"]]; copyrightSign _ PW.Get[design, "copyrightSign"]; myName _ PW.Get[design, "myName"]; outer _ PGA144.MakeOuter[design, PadFrame[], RenamePadsProc]; innerPos.x _ PW.Size[outer].x-PW.Size[inner].x; -- hack innerPos.y _ Onion.Center[inner, outer].y; eu _ Onion.LRSRoute[design, inner, outer, innerPos, layersParams].cell; PW.IncludeInCell[design, eu, copyrightSign, [-500*l, 0], 2]; PW.IncludeInCell[design, eu, myName, [PW.Size[eu].x+300*l, 0], 6]; END; EuControl.InitEUControl[design]; RETURN[MakeCompleteEu[]]; END; PW.Register[MakeEU, "Execution Unit"]; END. öEu.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Last Edited by: Monier, July 8, 1985 9:30:19 pm PDT -- Descriptors for the pad frame -- A large via of specified size, with a 10l extension of m2 on the left, m1 on the right -- Start with an empty cell of appropriate interestRect (origin in 0,0) -- Parse the pins and make the bridge -> vdd in m2, gnd in m1 -- Assemble the datapath and control -- Add the power bus on the right -- Specify the types of the items composing the pad frame descriptor -- This generates a standard pad frame; Pradeep will use the same one, so that we can share probe cards -- Prepares the inside of the EU for routing by Onion -- Generate the eu -- Generate the logo -- Generate the pad frame -- Position the eu, vertically centered, right flushed -- Include the logo (in the pad frame) MakeQuickCompleteEu: PROC RETURNS [eu: PW.ObPtr] = BEGIN inner, outer: CD.ObPtr; innerPos: CD.Position; layersParams: Onion.LayersParameters _ Onion.defaultLayersParameters; layersParams.wireExtendProc _ Onion.WireExtendPolToMetForPads; PW.SetDefaultSource[design, NIL]; inner _ Onion.MakeInner[design, RenameInnerPins[design, PW.Get[design, "eu"]]]; outer _ PGA144.MakeOuter[design, PadFrame[], RenamePadsProc]; -- Position the eu, vertically centered, right flushed innerPos.x _ PW.Size[outer].x-PW.Size[inner].x; -- hack innerPos.y _ Onion.Center[inner, outer].y; eu _ Onion.LRSRoute[design, inner, outer, innerPos, layersParams].cell; -- Include the logo!!! (maybe in the pad frame) END; RETURN[PadFrame[]]; RETURN[PGA144.MakeOuter[design, PadFrame[], RenamePadsProc]]; RETURN[EUIncreasingGen[]]; RETURN[MakeQuickCompleteEu[]]; RETURN[EuGen.RAMGen[design]]; RETURN[EuGen.BitLinesMuxesGen[design]]; RETURN[EuGen.BitLinesReadWriteGen[design]]; RETURN[EuGen.DrivekBusGen[design]]; RETURN[EuGen.AdrRegGen[design]]; RETURN[EuGen.FDRegsGen[design]]; RETURN[EuGen.PipeLineRegsGen[design]]; RETURN[EuGen.FieldUnitGen[design]]; RETURN[EuGen.ALUGen[design]]; RETURN[EuGen.ResultRegsGen[design]]; Ê*˜– "Cedar" stylešœ™Jšœ Ïmœ1™˜>Jšœ ˜ J™JšœL˜LJ™Jšžœžœ˜;Jšœžœ˜0Jšœ žœ˜"J™Jšœ=˜=J™6Jšœ žœžœ¢˜7Jšœ*˜*JšœG˜GJ™&Jšžœ0¡œ ˜™>J™Jšžœžœ™!J™Jšœ8žœ™OJšœ=™=J™6Jšœ žœžœ¢™7Jšœ*™*JšœG™GJ™/J™Jšžœ™—J˜Jšœ ˜ Jšžœ ™Jšžœ7™=Jšžœ™Jšžœ˜Jšœ™Jšžœ™Jšžœ!™'Jšžœ%™+Jšžœ™#Jšžœ™ Jšžœ™ Jšžœ ™&Jšžœ™#Jšžœ™Jšžœ™$Jšžœ˜—Jšžœ$˜&Jšžœ˜—J™—…—æ)