CSL Notebook Entry
To From
Recipients Louis Monier
 PARC
Subject Date
Pads design April 10, 1985 3:01:05 pm PST
Release as TargetFileName
Came from WorkingFileName ([Indigo]<Cedar®>Forms>CSLNotebook.form)
Last edited by Monier, April 10, 1985 3:01:32 pm PST
Abstract A collections of guidelines for designing pads, particularly aimed at our 2m CMOS process.
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Introduction
This is an attempt to gather most of the free-floating information bout pads design.
Input protection against ESD
Electro-static discharge can spoil your day. On a nice dry day, anyone rubbing its rubber soles on a carpet before handling a chip carrier can produce a discharge of several thousands volts. A human body in this condition is modeled as a 100pF capacitor connected to the fingertip through a 1500W resistor, and conventionnaly charged to 2000V. This is 100mJ, not enough to fry an egg, but if you force this energy down a pad in less than 100ns (several hundreed watts of instant power), what can happen? Three things:
 Something melts. Usually the first piece of conductor encountered whose resistance is too large for its size: too much heat is generated in too small a volume, and smoke follows.
 Zap! Enough tension reaches a gate to puncture the thin oxide. Our transistors do not stand more than 20V because the thin oxide is only 300A thick.
 Latchup! Somehow enough charge is injected in the substrate to initiate a latchup. Since pads carry large transistors and hefty power busses, this latchup usually results in the destruction of the chip.
None of these events are desirable, and pads must incorporate enough protection devices to allow a pad to survive the situation mentionned above.
Voltage limitation
It is important that no voltage greater than ~15V be applied to a gate. The best protection is an input serie resistor with a clamping device, shunting excessive voltage. The optimum value for the resistor is about 2kW, even though nobody seems to figure out why this empirical value works so well.
Resistor
A diffused resistor is best because it combines a resistor with a shunt diode. Polysilicon rersistor should be avoided, because of its poor thermal behavior. Transistor in punch-through mode are also used .
Diode
Any area of diffusion will act as a diode. A N+/substrate diode will turn on if the voltage is below -0.7V. In our technology, the superficiel resistivity of the substrate is high, and the diode is in serie with a resistor which limits its current sinking capability. One alternative is to use a piece of N-well, pinched by grounded P+ diffusion, as a similar diode with better caracteristics.
Similarly, a P+/N-well diode will turn on if the voltage is more than 0.7V above the power supply.
Transistor in punch-through mode
If we ground the gate and source of an n-type transistor and connect its drain to the input to protect, the transistor will turn on if the voltage is below -Vth, and will punch-through if V>some value. This type of protection was used in NMOS pads, but it seems that diodes turn on faster and sink more current. However, on an output pad, the large output transistors behave that way, and offer an extra free protection. Moreover, the diffusion on the drain side of the transistor acts as a diode. Actually, the gate is used only to bring the two pieces of diffusion close together. Two parallel diffusion wires will act similarly in punch-through mode. This is sometimes used between Vdd and Gnd rails to absorb spikes in the power lines before they reach the circuitry. Also increases the capacity of the power-distribution net, which is usually a good idea..
Metal-gate transistor
Usually turns on at a much higher voltage (20V or so for us, which might be too late), and sink negligable current. Don't use them.
Spark-gap
If you want your chip to survive a nuclear attack, use spark gaps. Two (sharp) metal structures separated by a few microns of dry air will initiate a spark if the voltage exceeds 300V. Somehow destructive (metal erosion is rapid). Also the necessary cut in the overglass brings contamination problems. Leave this to the military.
Heat diffusion
The worst place to dissipate a discharge is a polysilicon wire: high resistivity, and excellent thermal insulation by the oxides from the substrate or from the airflow, make it melt easily. Polysilicon contacts are a favorite rupture place.
The best place to dissipate heat is probably diffusion, because of its excellent thermal coupling to the substrate. N-well is even better, since it is deeper than N+ or P+. It is important to maximize the perimeter of diffusion, in order to increase the size of the contact to the substrate. Use many contacts between metal and diffusion, and a wide path to carry the input signal for the initial peak current may reach 700mA.
Latchup prevention
Any forwardbiased diode connected to the substrate will inject charges in it, and without protection, this might be enough to cause a nearby device to latchup. The known remedies:
Separation
Separate as much as possible the N+ and P+ diffusions. It is a good idea to have the pull-up and pull-down transistors of an output pad located on each side of the bonding area.
Guard rings
The most effective: in the N-well, a N+ guard ring connected to Vdd. Then a grounded P+ guard ring in the substrate. Finally, in case of absolute paranoia, a ring of N-well and N+ connected to Vdd, and acting as a pseudo-collector.
Layout Precaution
Spike induction: the metal wire connected to the pad should not overlap any unrelated poly or diffusion, because capacitive coupling could induce a spike, or break down the field oxide.
Input
The signal is amplified before been distributed to the circuit. We assume a load equivalent to 1pF (more than enough to transport a signal accross a chip. The first inverter is minimal since it is driven through a ~2KW resistance.
Output driving capability
The output pads should drive a 50pF bus in 5ns. The choice of drivers —300/2 n-type pull-down, and 600/2 p-type pull-up— insures a delay of about 6ns, which is OK.
Assuming that the pad drive the bus every 50ns, the average intensity through the power buses is 50pF*5V/50ns=5mA. The peak current reaches 40mA (estimated and measured on a simulation).
Electromigration
The average current is 5mA. If we connect 16 pads in a row the average intensity of 80mA necessitates a bus of width 80m in metal1, or 106m in metal2. By the way, this means that double bonding is mandatory if a single power pad must feed 32 pads, or an average current of 160mA.
Voltage drop
The resistance of the bus is about 2W. At peak current (640mA), the voltage drop is over 3V, which represent a very big bounce. Don't panic: the drivers won't turn on that fast, the various inductances will slow down the spike, and it does not really matter, because the rest of the chip is decoupled from the pad power supply.
In conclusion, we choose a bus of width 150m to power 16 pads, and hope for the best.
Geometrical considerations
Pitch
In our process, a 200m pitch is minimum. In a large chip with say 2 32-bit busses (the typical Dragon chip), some control wires and a lot of power pads, the pins count easily approach 140. This means 28mm, or 7mm on the side. Actually there is more to fit in the pad frame: double bonding of power pads, clock generator, . . . This means that a narrow pitch is a good idea, givent that most chips are pad-limited.
The bonding area (combination of m1, m2, via and cut in the overglass) is 106m in diameter, with a 10m extension on each side. Bonding a wire is not a gentle activity, so it is better to keep any unrelated geometry at least 25m away from the bonding area. This leaves a 200 - 126 - 2 * 25 = 24m wide region to play with. . . The bonding area is located outside the chip, which reduces the length of the bonding wire: lower inductance, better separation of wires.
Description of the Cmos Pad Library for the PGA144
Pitch 200m. The pad uses four power tracks: PadGnd, PadVdd, Gnd, and Vdd, stacked to save space and help reduce the inductance. From the outside to the inside of the chip we find: bonding pad, output drivers, power buses for the output drivers, logic, and power buses for the chip.
PadVdd is in metal2 and on top of PadGnd which runs in metal1. Width 150m. Idem for Vdd and Gnd. The width depends on the need in current of the circuit.
Input Protection
A P+/N-well resistor followed by a N-well/grounded P+ resistor. Total resistance is about 2KW. Guard rings and enough distance between the devices to prevent latchup in nearby drivers. The source of the drivers also acts as a diode, and the drivers (when present) as transistors in punch-through mode.
Output