DragOpsCross: CEDAR DEFINITIONS = BEGIN
wordsPerPage:	CARDINAL = 1024;
bytesPerWord:	CARDINAL = 4;
charsPerWord:	CARDINAL = 4;
bitsPerByte:	CARDINAL = 8;
bitsPerCharacter:	CARDINAL = 8;
bitsPerWord:	CARDINAL = bitsPerByte*bytesPerWord;
bytesPerPage:	CARDINAL = wordsPerPage*bytesPerWord;

logWordsPerPage:	CARDINAL = 10;  -- LogBase2[wordsPerPage]
logBitsPerByte:	CARDINAL = 3;  --LogBase2[bitsPerByte]
logBitsPerChar:	CARDINAL = 3;  --LogBase2[bitsPerCharacter]
logBytesPerWord:	CARDINAL = 1;  --LogBase2[bytesPerWord]
logCharsPerWord:	CARDINAL = 1;  --LogBase2[bytesPerWord]
logBitsPerWord:	CARDINAL = logBitsPerByte + logBytesPerWord;
logBytesPerPage:	CARDINAL = logBytesPerWord + logWordsPerPage;

PageCount:	TYPE = INT;
PageNumber:	TYPE = INT;

maxPagesInVM:	PageCount = LONG[4]*LONG[1024]*LONG[1024];

SixBitIndex:	TYPE = [0..64);

FiveBitIndex: TYPE = [0..32);
Word: TYPE = PACKED ARRAY FiveBitIndex OF BOOL;
ZerosWord: Word = LOOPHOLE[LONG[0]];
OnesWord: Word = LOOPHOLE[LONG[-1]];
TwoWords: TYPE = ARRAY [0..1] OF Word;

FourBitIndex: TYPE = [0..16);
Half: TYPE = PACKED ARRAY FourBitIndex OF BOOL;
ZerosHalf: Half = LOOPHOLE[0];
OnesHalf: Half = LOOPHOLE[-1];
ThreeBitIndex: TYPE = [0..7];
FourHalves: TYPE = ARRAY [0..3] OF Half;
TwoHalves: TYPE = ARRAY [0..1] OF Half;

Byte: TYPE = PACKED ARRAY ThreeBitIndex OF BOOL;
ZerosByte: Byte = LOOPHOLE[0];
OnesByte: Byte = LOOPHOLE[377B];
EightBytes: TYPE = PACKED ARRAY [0..7] OF Byte;
FourBytes: TYPE = PACKED ARRAY ByteIndex OF Byte;
ByteIndex: TYPE = [0..bytesPerWord);
BytesPerWord: NAT = 4;
TwoBytes: TYPE = PACKED ARRAY [0..1] OF Byte;

Comparison: TYPE = MACHINE DEPENDENT {less(0), equal(1), greater(2)};

ByteAddress: TYPE = RECORD [Word];

WordAddress: TYPE = RECORD [Word];
FieldDescriptor: TYPE = MACHINE DEPENDENT RECORD [
reserved: [0..7] _ 0,
insert: BOOL _ FALSE,
mask: [0..32] _ 32,
shift: [0..32] _ 0
];

RegIndex: TYPE = [0..16);
PadByte: TYPE = [0..255];
Lit8: TYPE = [0..255];
Op4: TYPE = [0..15];
Op8: TYPE = [0..255];
JDist8: TYPE = [0..255];

Inst: TYPE = MACHINE DEPENDENT {
dTrap	(000B),
dLC0	(20B),	dLC1,	dLC2,	dLC3,	dLC4,	dLC5,	dLC6,	dLC7,
x060B	(060B),	dDFC,	dLIQB,	x063B,	x064B,	x065B,	dJ5,	dJQB,
dOR	(100B),	dAND,	dRX,	dBC,	dADD,	dSUB,	dLADD,	dLSUB,
dDUP	(110B),	dDIS,	x112B,	dEXDIS,	dSFC,	dSFCI,	dRETN,	x117B,
x120B	(120B),	x121B,	x122B,	x123B,	dKFC,	x125B,	dJ1,	dJS,
dLR0	(140B),	dLR1,	dLR2,	dLR3,	dLR4,	dLR5,	dLR6,	dLR7,
dLR8	(150B),	dLR9,	dLR10,	dLR11,	dLR12,	dLR13,	dLR14,	dLR15, 
dSR0	(160B),	dSR1,	dSR2,	dSR3,	dSR4,	dSR5,	dSR6,	dSR7,
dSR8	(170B),	dSR9,	dSR10,	dSR11,	dSR12,	dSR13,	dSR14,	dSR15,

dQOR	(200B),	dQAND,	dQRX,	dQBC,
dQADD	(204B),	dQSUB,	dQLADD,	dQLSUB,
dALS	(210B),	dAL,	dASL,	dAS,	dCST,	x215B,	dRET,	dRETK,
dLIP	(220B),	dSIP,	dLIB,	x223B,	dADDB,	dSUBB,	dJ2,	dJB,
dRB	(230B),	dWB,	dRSB,	dWSB,	x234B,	x235B,	x236B,	dPSB,
dLRI0	(240B),	dLRI1,	dLRI2,	dLRI3,	dLRI4,	dLRI5,	dLRI6,	dLRI7,
dLRI8	(250B),	dLRI9,	dLRI10,	dLRI11,	dLRI12,	dLRI13,	dLRI14,	dLRI15,
dSRI0	(260B),	dSRI1,	dSRI2,	dSRI3,	dSRI4,	dSRI5,	dSRI6,	dSRI7,
dSRI8	(270B),	dSRI9,	dSRI10,	dSRI11,	dSRI12,	dSRI13,	dSRI14,	dSRI15,

dROR	(300B),	dRAND,	dRRX,	dRBC,
dRADD	(304B),	dRSUB,	dRLADD,	dRLSUB,
dRXOR	(310B),	x311B,	dRFU,	x313B,
dRVADD	(314B),	dRVSUB,	dRUADD,	dRUSUB,
dLGF	(320B),	dLFC,	dLIDB,	x323B,
dADDDB	(324B),	dSUBDB,	dJ3,	dJDB,
dRAI	(330B),	dWAI,	dRRI,	dWRI,
dIOS	(334B), 	dIOL,	dION,	x337B,

x340B	(340B),	dRJEB,	dRJLB,	dRJLEB,
x344B	(344B),	dRJNEB,	dRJGEB,	dRJGB,
x350B	(350B),	dRJNEBJ,	dRJGEBJ,	dRJGBJ,
x354B	(354B),	dRJEBJ,	dRJLBJ,	dRJLEBJ,

dJEBB	(360B),	dJNEBB,	dJEBBJ,	dJNEBBJ,
x364B	(364B),	x365B,	x366B,	x367B,

dSHL	(370B),	dSHR,	dSHD,	dFSDB,
x374B	(374B),	x375B,	x376B,	x377B};

dFirst: Inst = FIRST[Inst];
dLast: Inst = LAST[Inst];
OIformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
pad: PadByte _ 0
];
OQBformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
b0,b1,b2,b3: Lit8,
pad: PadByte _ 0
];
LRformat: TYPE = MACHINE DEPENDENT RECORD [
op: Op4, reg: RegIndex,
pad: PadByte _ 0
];
QRformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
aOp: ShortRegQR,
opt,aux: BOOL, reg: RegIndex
];
ShortRegQR: TYPE = MACHINE DEPENDENT {
topAtop(0),	-- C:   [S],    A: [S], B: general
pushAtop(1),	-- C: [S+1]+, A: [S], B: general
pushA0(2),	-- C: [S+1]+, A: c0, B: general
pushA1(3)};	-- C: [S+1]+, A: c1, B: general
OBformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
lit: Lit8
];
LRBformat: TYPE = MACHINE DEPENDENT RECORD [
op: Op4, reg: RegIndex,
lit: Lit8
];
RRformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
aOpt,cOpt,bOpt,aux: BOOL, b: RegIndex,
c,a: RegIndex,
pad: PadByte _ 0
];
ODBformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
lit0: Lit8,
lit1: Lit8,
pad: PadByte _ 0
];
LRRBformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
disp: Lit8,
reg1,reg2: RegIndex,
pad: PadByte _ 0
];
RJBformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
aOp: ShortRegRJB,
opt,aux: BOOL, reg: RegIndex,
dist: JDist8,
pad: PadByte _ 0
];
ShortRegRJB: TYPE = MACHINE DEPENDENT {
c0(0),	-- constant 0
c1(1),	-- constant 1
top(2),	-- [S]
popTop(3)};	-- [S]-
JBBformat: TYPE = MACHINE DEPENDENT RECORD [
op: Inst,
lit: Lit8,
dist: JDist8,
pad: PadByte _ 0
];

TrapWidthWords: NAT = 4;
TrapWidthBytes: NAT = TrapWidthWords*bytesPerWord;

XopBase: LONG CARDINAL = 1000000B;
TrapBase: LONG CARDINAL = XopBase+256*TrapWidthWords;
KernalLimit: LONG CARDINAL = 100000000B;

TrapIndex: TYPE = MACHINE DEPENDENT {

StackUnderflowTrap	(00B), -- called if RET* or ALS and IFU stack is empty 
IFUPageFaultTrap	(01B), -- called when IFU gets a page fault
ResetTrap	(07B), -- transfered to (no call) when RESET is asserted

IFUStackOverflowTrap	(10B), -- called when IFU stack fills
EUStackOverflowTrap	(11B), -- called when SP goes beyond SPlim
RescheduleTrap	(12B), -- called when RESCHEDULE is acknowledged


ALUCondFalse	(20B),  -- ALU fault FALSE
ALUCondEZ	(21B),  -- ALU fault = (zero)
ALUCondLZ	(22B),  -- ALU fault < (zero)
ALUCondLE	(23B),  -- ALU fault <= (zero)
AddressCheckFault	(24B),  -- Kernel address from user mode (see PBus cmd) 
ALUCondNE	(25B),  -- ALU fault = (zero)
ALUCondGE	(26B),  -- ALU fault >= (zero)
ALUCondGZ	(27B),  -- ALU fault > (zero)
ALUCondOver	(30B),  -- ALU fault overflow  **
ALUCondBC	(31B),  -- ALU fault bounds check  **
ALUCondIL	(32B),  -- ALU fault illegal Lisp number  **
ALUCondDO	(33B),  -- ALU Division Overflow  **
ALUCondNotOver	(34B),  -- ALU fault NOT overflow
ALUCondNB	(35B),  -- ALU fault NOT bounds check
ALUCondNI	(36B),  -- ALU fault NOT illegal Lisp number
ModeFault	(37B),  -- Kernel instruction attempted in user mode


EUPageFault	(41B), -- when DPbus indicates EU Cache page fault
EUWriteFault	(42B), -- when DPbus indicates EU Cache write protect fault
AUFault	(43B)}; -- when DPbus indicates AU fault

ProcessorRegister: TYPE = MACHINE DEPENDENT {
euStack	(0),    -- beginning of EU Stack
euJunk	(128), -- the non-matching EU register
euToKBus	(129), -- send result on K bus to IFU
euMAR	(130), -- MemoryAddressRegister
euField	(131), -- Field register
euConstant	(132), -- Base of EU constant registers	(12 regs)
euAux	(144), -- Base of EU aux registers	(16 regs)
euBogus	(160), -- [euBogus..euLast] not legal  (NA)	(80 regs)
euLast	(239), -- last possible EU reg  (NA)

ifuYoungestL	(240), -- youngest L in IFU stack
ifuYoungestPC	(241), -- youngest PC in IFU stack
ifuEldestL	(242), -- eldest L in IFU stack
ifuEldestPC	(243), -- eldest PC in IFU stack (rd removes, wt adds)
ifuStatus	(244), -- IFU status
ifuSLimit	(245), -- stack limit register

ifuBogus	(246), -- [ifuBogus..ifuLast] are not legal  (NA)
ifuL	(252), -- current L register (NA)
ifuS	(253), -- current S register (NA)
ifuPC	(254), -- current program counter (NA)
ifuLast	(255)  -- last possible IFU reg  (NA)
};

EURegs: TYPE = ProcessorRegister[euStack..euLast];
EULegalRegs: TYPE = ProcessorRegister[euStack..euBogus);
IFURegs: TYPE = ProcessorRegister[ifuYoungestL..ifuLast];
IFULegalRegs: TYPE = ProcessorRegister[ifuYoungestL..ifuBogus);


IFUStatusRec: TYPE = MACHINE DEPENDENT RECORD [
pad0		(0:00..07):	[0..255]	_ 0,
pad1		(0:08..15):	[0..255]	_ 0,
version		(0:16..23):	[0..255]	_ 0,	-- IFU version number
spareKeep	(0:24..24):	BOOL	_ FALSE,	-- when writing, keep old value
spareBit		(0:25..25):	BOOL	_ FALSE,	-- not used right now
userModeKeep	(0:26..26):	BOOL	_ FALSE,	-- when writing, keep old value
userMode	(0:27..27):	BOOL	_ FALSE,	-- TRUE => user, FALSE => kernel
trapsEnabledKeep	(0:28..28):	BOOL	_ FALSE,	-- when writing, keep old value
trapsEnabled	(0:29..29):	BOOL	_ FALSE,	-- TRUE => traps enabled
rescheduleKeep	(0:30..30):	BOOL	_ FALSE,	-- when writing, keep old value
reschedule	(0:31..31):	BOOL	_ FALSE	-- TRUE => reschedule pending
];

IFUStackIndex: TYPE = [0..IFUStackSize);
IFUStackSize: NAT = 15;
IFUOverflow: NAT = 12;

EUStackIndex: TYPE = [0..EUStackSize);
EUStackSize: NAT = 128;
EULocalIndex: TYPE = [0..EULocals);
EULocals: NAT = 16;
EUAuxIndex: TYPE = [0..EUAuxRegs);
EUAuxRegs: NAT = 16;
EUConstIndex: TYPE = [0..EUConstants);
EUConstants: NAT = 12;

IOLocation: TYPE = LONG CARDINAL;


ioRescheduleRequest: IOLocation = 1000000B;


ioResetRequest: IOLocation = 1000001B;
IOOperand: TYPE = MACHINE DEPENDENT RECORD [
pDataA: Byte _ ZerosByte, -- IO address or address offset
pCmd: PCmdFormat _ [] -- PBus command
];

PCmdFormat: TYPE = MACHINE DEPENDENT RECORD [
register: PCmdRegister _ first,
mode: PCmdMode _ any,
addressChecks: PCmdAddressChecks _ none,
direction: PCmdDirection _ read
];

PCmdRegister: TYPE = MACHINE DEPENDENT {
first (00B),
last (37B)
};
PCmdMode: TYPE = MACHINE DEPENDENT {any(0), kernelOnly(1)};
PCmdAddressChecks: TYPE = MACHINE DEPENDENT {none(0), kernelIfFirst16M(1)};
PCmdDirection: TYPE = MACHINE DEPENDENT {read(0), write(1)};


END.


���,��DragOpsCross.mesa
Copyright c 1984, 1985, 1986 by Xerox Corporation.  All rights reserved.
Russ Atkinson (RRA) April 1, 1986 5:03:21 pm PST
Curry, September 12, 1985 10:46:26 pm PDT
McCreight, January 8, 1986 3:37:59 pm PST
This interface consists exclusively of type definitions for the architectural data structures of the Dragon Mesa processor.  A prose description of the instruction set is kept as DragOps.tioga.  A companion interface, DragOpsCrossUtils, provides convenient operations (usually inline) for manipulating Dragon values on PrincOps machines.

These definitions are tentative, and are largely analogous to the Cedar PrincOps.  Especially tentative definitions are marked by (??).  Where LONG POINTER appears, it should be taken as a comment, and Word values should be used to actually build such structures for Dragon.
Basic Types and Associated Values
actually, [0..maxPagesInVM]; intended for use by VM
actually, [0..maxPagesInVM); intended for use by VM
22-bit page index
We would like to use ALL[FALSE], but the compiler is really stupid
We would like to use ALL[TRUE], but the compiler is really stupid
This type is the type to be returned from comparison operations.
To be used to denote byte addresses, when the difference between bytes addresses and other words needs to be indicated.
To be used to denote word addresses, when the difference between addresses and other words needs to be indicated.
Field descriptor formats
A field descriptor is a special interpretation of a 16-bit quantity used to control the Field Unit.  In the Field Unit, the shifter takes two words in and produces one word appropriately shifted to the left.  The mask is used as a multiplexor to select bits from either the shifter output or the background word.

reserved bits, not currently used, but must be 0s
governs choice of background and low bits of mask
32-mask gives start pos of 1s in the mask (mask = 0 => no 1s)
gives # of bits to left-shift the double word
Instruction Set
(wizards only, current opcode assignments are probably wrong)

Instruction formats are padded to 16 bit boundary to keep the compiler happy.
valid register index for locals, aux, etc.
padding byte
8-bit literal or displacement
4-bit opcode
8-bit opcode
jump distance interpreted as signed byte
Leftmost bits of opcode determine length of instruction.
000 => 1 byte	(1 byte traps)
001 => 5 bytes	[040B..077B]
01- => 1 byte	[100B..177B]
10- => 2 bytes	[200B..277B]
11- => 3 bytes	[300B..377B]
Leftmost bits of opcode determine possible PC displacement selection.
0-------	PC + stack		JS
10------	PC + alphaS		JB
110-----	PC + alphaBetaS		JDB and LFC
111-----	PC + betaS		RJB's and JBB's

One byte traps (system calls, really)

OIformat (1 byte)

OQBformat (5 bytes)

OIformat (1 byte)

LRformat (1 byte)
QRformat (2 bytes)

OBformat (2 bytes)

LRBformat (2 bytes)
RRformat (3 bytes)

ODBformat and LRRBformat (3 bytes) 
RJBformat (3 bytes)
JBBformat (3 bytes)
ODBformat (3 bytes)
OIformat (1 byte)
OQBformat (5 bytes)
LRformat (1 byte)
QRformat (2 bytes)
Short encoding for C and A operands of the QR format instructions.  The B operand is always a general operand.

OBformat (2 bytes)
LRBformat (2 bytes)
RRformat (3 bytes)
ODBformat (3 bytes)
LRRBformat (3 bytes)
RJBformat (3 bytes)
Short encoding for A operand of RJB instruction.

JBBformat (3 bytes)
Trap Assignments
These declarations are made with LONG CARDINAL to permit the compiler to do arithmetic with them.  The compiler is not bright enough to do arithmetic with type Word.
each trap is TrapWidthWords words from the previous trap
each trap is TrapWidthBytes words from the previous trap
base word addr of Xop traps.  There is space for 256 of them, although most are unused.
base word addr of other traps.  There is one for each trap in TrapIndex.
tentative limit for Kernel addressing
There are 4 trap quadrants of 16 traps each (last quad not currently used).  Note that not all trap indexes can occur through use of the instruction set.  The assignments are chosen to make the IFU simpler.  The word address of transfer for trap X is TrapBase+TrapWidthWords*X.
TrapQuad0:  
The 6 Traps in TrapQuad0 cause further maskable traps to be disabled.  Only the second eight trap locations in TrapQuad0 are maskable.

TrapQuad1:  ALU Condition Test Traps
ALU traps correspond to ALU Dragon.CondSelects in [Indigo]<Dragon>Rosemary>Dragon.mesa.  The traps that the current instruction set sees are starred (**).  Most of the other conditions are used to influence conditional jumps.  These traps are not maskable.
	            (must be 37B, see McCreight)
TrapQuad2:  DPBus Cache and Arithmetic Unit Faults
EU Cache PBus fault traps:  Only page fault and write protect fault are visible at the instruction set level.  These traps are not maskable.
Processor Register Numbers (tentative)
These assignments are to be used with the LIP, and SIP instructions.  We use the ProcessorRegister declarations for both IFU and EU parts.

There are actually more assignments than are accessible through these instructions.  These are marked by (NA), which indicates that the decode is reserved for the register, but that the data paths to allow the register to be used are not present.
These IFU register addresses are noticed within the IFU. Destinations are changed to references to the "toKBus" register.  Sources are changed so that ALURightSource (an EU control input) = kBus.
The rest of these registers, if they exist, aren't accessible at these addresses.
unfortunately includes illegal cases: [euSpare0..euUseK]
Status register declarations  (??)
The status register has 3 two bit fields.  When writing to the status register, the MSB of each field controls whether the LSB of the field is to be preserved(1) or changed(0).  When reading from the status register, the preserve bit will always be false so that writing the word back restores the state.  Writing Zero to the status register clears it.
IFU register stack
The number of frames in the stack is IN [0..IFUStackSize]
If traps are enabled then control arrives at the IFU stack overflow handler with exactly IFUOverflow frames on the stack. 
EU register stack

EU local variable register

EU auxilliary register stack

EU constant register stack
Special I/O locations
These assignments are to be used with the IO* instructions.  All of these locations are quite speculative right now.  All IO locations are declared as if they were word addresses, but are expressed in terms that make it easy to declare constants.  Just remember to translate them to type Word when necessary.
a word address
Reschedule request location.  Writing anything into this location requests a reschedule interrupt.  The exact mechanism is undefined.
Reset request location.  Writing anything into this location requests a system reset.  The exact mechanism is undefined.
IO operand types
The register assignments are not yet specified.  For now we just reserve the space.
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