-- Precharge PLA Module Generator File: DragonMicroPLA.mg

Last Edited by: Twilliams, August 23, 1984 9:08:00 pm PDT

ModuleGenerator ← "MakePLA";

TruthTableFile ← "///Users/Twilliams.pa/DragonMicroPLA.tt";

Extras ← 8;

NoStretch ← TRUE;

TileSet ← "/Ivy/Twilliams/PLA/PLAcontrolTiles.dale";

Inputs ← state op alpha beta delayACycle iStkEmpty pushPending popPending instReady

Outputs ← LIST[ "aReg.bit0", "aReg.bit1", "aReg.bit2", "aReg.bit3", "aReg.bit4", "aReg.bit5", "aReg.bit6", "bReg.bit0", "bReg.bit1", "bReg.bit2", "bReg.bit3", "bReg.bit4", "bReg.bit5", "bReg.bit6", "getNextMacro", "xBSource.bit0", "xBSource.bit1", "xBSource.bit2", "xBSource.bit3", "doMacroJump", "cReg.bit0", "cReg.bit1", "cReg.bit2", "cReg.bit3", "cReg.bit4", "cReg.bit5", "cReg.bit6", "lSource.bit0", "lSource.bit1", "lSource.bit2", "lSource.bit3", "lSource.bit4", "lSource.bit5", "lSource.bit6", "sSource.bit0", "sSource.bit1", "sSource.bit2", "sSource.bit3", "sSource.bit4", "sSource.bit5", "sSource.bit6", "deltaSa", "deltaSb", "deltaSc", "xASource.bit0", "xASource.bit1", "xASource.bit2", "xASource.bit3", "aluRtIsK", "aluOp.bit0", "aluOp.bit1", "aluOp.bit2", "aluOp.bit3", "aluOp.bit4", "condSel.bit0", "condSel.bit1", "condSel.bit2", "condSel.bit3", "condEffect.bit0", "condEffect.bit1", "dontBypass", "iStackPostEffect.bit0", "iStackPostEffect.bit1", "iTrapPostEffect.bit0", "iTrapPostEffect.bit1", "euPBusCmd.bit0", "euPBusCmd.bit1", "euPBusCmd.bit2", "euPBusCmd.bit3", "pipedPLSASpec.bit0", "pipedPLSASpec.bit1", "pushLevel3", "delayed"];

OutputLocations ← LIST["100", "200", "300", "400", "500", "600", "700", "800", "900", "1000", "1100", "1200", "1300", "1400", "1500", "1600", "1700", "1800", "1900", "2000", "2100", "2200", "2300" ];

TruthTableDumpFile ← "///Users/Twilliams.pa/DragonPLA.dump";