DMSmallCacheModelImpl:
CEDAR
PROGRAM
IMPORTS DMPBusModel, DragOpsCrossUtils, IO, PrintTV
EXPORTS DMSmallCacheModel
= BEGIN OPEN DMSmallCacheModel;
lineAdrs: LineName;
lineAdrsValid: BOOL;
Create:
PUBLIC
PROC [pbus, mbus:
DM.Component]
RETURNS [cache:
DM.Component] = {
ctlAB, ctlBA, mra, sla, mrqa, aa, wsa: DM.Component;
First create the subcomponents, then create the cache itself
cache ←
NEW [
DM.ComponentRec ← [
action: [Reset, PhA, EvPhA, PhB, EvPhB],
history: NIL,
componentType: $SmallCache,
subComponents: NIL,
specific:
NEW [CacheSpecificRec ← [
pbus: pbus,
mbus: mbus
]]
]];
};
PhA:
DM.ActionProc = {
cs: CacheSpecific ← NARROW[component.specific];
cache.state.mbusHasSC ← ??;
};
EvPhA:
DM.ActionProc = {
cs: CacheSpecific ← NARROW[component.specific];
cs.pbusOp ← DMPBusModel.Cmd[cs.pbus];
IF cs.mbusHasSC
THEN {
}
ELSE MatchCam[cs];
};
PhB:
DM.ActionProc = {
cs: CacheSpecific ← NARROW[component.specific];
IF cs.pbusOp = Fetch THEN DMPBusModel.DrData[cs.pbus, ReadRam[cs]];
DMPBusModel.DrReject[cs.pbus, Reject[cs]]
};
EvPhB:
DM.ActionProc = {
cs: CacheSpecific ← NARROW[component.specific];
IF (DMPBusModel.Cmd[cs.pbus] = Store)
AND (~ cs.mbusHasSC)
THEN WriteRam[cs, DMPBusModel.Data[cs.pbus]]
};
Reset:
DM.ActionProc = {
cs: CacheSpecific ← NARROW[component.specific];
cs.mbusHasSC ← FALSE;
FOR i: INT IN [1..cs.nLines] DO cs.cam[i].valid ← FALSE ENDLOOP;
Initialize the locations that will be read and written
cs.cam[1].valid ← TRUE;
cs.cam[1].va ← DragOpsCrossUtils.IntToWord[1];
cs.cam[1].shared ← FALSE;
cs.cam[1].master ← FALSE;
cs.cam[2].valid ← TRUE;
cs.cam[2].va ← DragOpsCrossUtils.IntToWord[2];
cs.cam[2].shared ← FALSE;
cs.cam[2].master ← FALSE;
cs.cam[3].valid ← TRUE;
cs.cam[3].va ← DragOpsCrossUtils.IntToWord[3];
cs.cam[3].shared ← FALSE;
cs.cam[3].master ← FALSE;
PrintTV.RegisterTVPrintProc[type: CODE[RamType], proc: PrintRam];
PrintTV.RegisterTVPrintProc[type: CODE[CamType], proc: PrintCam];
};
MatchCam:
PROC [cs: CacheSpecific] = {
lineAdrsValid ← FALSE;
FOR i:
INT
IN [1..cs.nLines]
DO
IF cs.cam[i].va = DMPBusModel.Data[cs.pbus]
THEN {
lineAdrsValid ← TRUE; lineAdrs ← i; RETURN}
ENDLOOP;
};
PrintCam: PrintTV.TVPrintProc = {
[tv: TV, data: REF ANY, stream: STREAM, depth: INT ← 4, width: INT ← 32, verbose: BOOL ← FALSE] RETURNS [useOld: BOOL ← FALSE]
stream.PutF["cam: ... "]
};
ReadRam:
PROC [cs: CacheSpecific]
RETURNS [data:
DM.Word] = {
IF lineAdrsValid THEN RETURN [cs.ram[lineAdrs]];
};
WriteRam:
PROC [cs: CacheSpecific, value:
DM.Word] = {
IF lineAdrsValid THEN cs.ram[lineAdrs] ← value;
};
PrintRam: PrintTV.TVPrintProc = {
[tv: TV, data: REF ANY, stream: STREAM, depth: INT ← 4, width: INT ← 32, verbose: BOOL ← FALSE] RETURNS [useOld: BOOL ← FALSE]
stream.PutF["ram: ... "]
};
Reject:
PROC [cs: CacheSpecific]
RETURNS [
BOOL] = {
RETURN[
~lineAdrsValid OR
cs.mbusHasSC];
};
END.