PORTS [
CSLd3AB < EnumType["DragonFP.CSLoad"],
CSUn2AB < EnumType["DragonFP.CSUnload"],
EPFaultB > EnumType["Dragon.PBusFaults"],
EPData = INT[32], -- X in during A, Z out during B
KBus = INT[32], -- F, L, U in during A
PhA, PhB < BOOL,
InstrCountAB < INT[32] -- For log
]
State
-- All state changes on down edge of PhA (ie are BA signals)
f0, f1, freg: DragonFP.Function,
mode: DragonFP.Mode,
x0, x1: Dragon.HexWord,
aM, aL, bM, bL: Dragon.HexWord,
arM, arL, brM, brL: Dragon.HexWord,
aluCSL1, mulCSL1: DragonFP.CSLoad,
aluCSU1, mulCSU1: DragonFP.CSUnload,
aluCSU2, mulCSU2: DragonFP.CSUnload,
load0, load1: DragonFP.Load,
unload0, unload1: DragonFP.Unload,
aluST0, mulST0: Dragon.PBusFaults,
aluST1, mulST1: Dragon.PBusFaults,
aluDM, mulDM: Dragon.HexWord,
aluDL, mulDL: Dragon.HexWord,
aluZ, mulZ: Dragon.HexWord
EvalSimple
IF PhA
THEN {
clocked ← FALSE;
load0 ← LOOPHOLE[BitOps.ECFD[KBus, 32, 16+ 2, 5]];
f0 ← LOOPHOLE[BitOps.ECFD[KBus, 32, 16+ 7, 1]];
unload0 ← LOOPHOLE[BitOps.ECFD[KBus, 32, 16+10, 6]];
x0 ← Dragon.LFD[EPData];
};
IF
NOT PhA
AND
NOT clocked
THEN {
clocked ← TRUE;
cycle ← MAX[cycle-1, -1]; -- off at -1
IF cycle=0 THEN
csU2 ← csU1;
SELECT type FROM
Alu => [[aluDM, aluDL], aluST0] ←
DragonFP.ALU [[arM,arL], [brM,brL], freg, mode, aArg, bArg];
Mult => [[mulDM, mulDL], mulST0] ←
DragonFP.MUL [[arM,arL], [brM,brL], freg, mode, aArg, bArg];
csU1 ← CSUn2AB;
IF CSUn2AB=unload
THEN
SELECT code
FROM
fpLdSglAUnMsw => {ibus ← dm};
fpLdLswAUnLsw => {ibus ← dl};
fpLdMswAUnMsw => {ibus ← dm};
ENDCASE => Dragon.Assert[FALSE, "Unimplemented unload code"] };
IF CSLd3AB=load
THEN {
SELECT code
FROM
fpLdSglBSt => {brS ← ibus; freg� start←TRUE};
fpLdLswB => {brL ← ibus; start←FALSE};
fpLdLswBSt => {brL ← ibus; freg� start←TRUE};
fpLdMswB => {brM ← ibus; start←FALSE};
fpLdMswBSt => {brM ← ibus; freg� start←TRUE};
fpLdSglAUnMsw => {arS ← ibus; unload←msw; start←FALSE};
fpLdLswAUnLsw => {arL ← ibus; unload←lsw; start←FALSE};
fpLdMswAUnMsw => {arM ← ibus; unload←msw; start←FALSE};
delGamBetAlp => mode ← DragonFP.SetMode[mode, f1];
ENDCASE => Dragon.Assert[FALSE, "Unimplemented load code"] };
aluZ ← IF unload1=msw THEN aluDM ELSE aluDL;
mulZ ← IF unload1=msw THEN mulDM ELSE mulDL;
unload1 ← unload0;
aluST1 ← aluST0;
mulST1 ← mulST0;
IF mulCSL1=load THEN { };
SELECT load1
FROM
none => { };
func => {arM𡤊M; arL𡤊L; brM𡤋M; brL𡤋L; freg�};
bLo => {arM𡤊M; arL𡤊L; brM𡤋M; brL𡤋L←x1; freg�};
bHi => {arM𡤊M; arL𡤊L; brM𡤋M←x1; brL𡤋L; freg�};
aLo => {arM𡤊M; arL𡤊L←x1; brM𡤋M; brL𡤋L; freg�};
aHi => {arM𡤊M←x1; arL𡤊L; brM𡤋M; brL𡤋L; freg�};
delGamBetAlp => mode ← DragonFP.SetMode[mode, f1];
ENDCASE => Dragon.Assert[FALSE, "Unimplemented load code"] };
The following assumes that the D regs can be made transparent - Check this
It may be that load nop's may be required between the load and unloads in order to make sure that D gets clocked. The timing is such that the nop load must occur one cycle before the unload which means that it must occur two cycles before the unload in the microcode stream since unloads are driven by IPipe one cycle before loads.
[[aluDM, aluDL], aluST0] ← DragonFP.ALU[[arM,arL], [brM,brL], freg, mode];
[[mulDM, mulDL], mulST0] ← DragonFP.MUL[[arM,arL], [brM,brL], freg, mode];
f1 ← f0;
x1 ← x0;
aluCSL1 ← FPCSLdAlu3AB;
mulCSL1 ← FPCSLdMult3AB;
load1 ← load0
};
IF PhB
THEN {
TEN is tied to phB'
IF aluCSU2=unload
THEN {
EPData ← Dragon.LTD[aluZ];
EPFaultB ← aluST1;
IF log #
IO.noWhereStream
THEN {
log.PutF["\n%5g", IO.card[ Dragon.LFD[InstrCountAB] ] ];
log.PutF[" FP-Alu:%08x", IO.card[ Dragon.LFD[EPData] ] ];
log.PutF[" Status:%01x", IO.card[ LOOPHOLE[aluST1, CARDINAL] ] ] } };
IF mulCSU2=unload
THEN {
EPData ← Dragon.LTD[mulZ];
EPFaultB ← mulST1;
IF log #
IO.noWhereStream
THEN {
log.PutF["\n%5g", IO.card[ Dragon.LFD[InstrCountAB] ] ];
log.PutF[" FP-Mul:%08x", IO.card[ Dragon.LFD[EPData] ] ];
log.PutF[" Status:%01x", IO.card[ LOOPHOLE[mulST1, CARDINAL] ] ] } };
};