Bland, February 18, 1986 12:46:32 pm PST
Copyright © 1985 by Xerox Corporation. All rights reserved.
/ivy/bland/doc/instructionSet.tioga
DRAFT
INSTRUCTIONSET - VERSION 3
FOR INTERNAL XEROX USE ONLY
3 INSTRUCTION SET
3.0 Notational Conventions
3.0.1 Semi-colons
In the instruction definitions, statements separated by semi-colons are executed sequentially. For example, the Add Byte (ADDB) instruction is described by the following equations:
1) Stack[S] ← Stack[S] + zExt[literal] + Carry;
2) Carry ← 0.
And the Interpretation of Operands for the Add Byte instruction is Signed. That is, the Carry referenced in the first equation is the Carry resulting from the previous operation. (See the definitions of Signed, Unsigned, Lisp, and Small Integer Arithmetic in section 2.2.1.) The Carry referenced in the second equation is the Carry resulting from Add Byte instruction itself. If that Add Byte instruction had resulted in integer overflow, an integer overflow trap instruction would have been taken. In any event, the Carry is set to 0 after the instruction is executed.
3.0.2 S
S is used to indicate the effect of the instruction on the stack pointer, S. S is set to zero at the beginning of each instruction. S is incremented by S after instruction execution.
3.0.3 Font Changes
In the instruction definitions, implicit and explicit operands are distinguished by a font change. Explicit operands are printed in TimesRoman (the normal font). Implicit operands are printed in Helvetica. When a bold typeface is used, the difference between the two fonts is fairly subtle. For example, in the following instruction, Stack[S+1] ← zExt[literal]; Stack[S+1], an implicit operand, is given in the Helvetica font and literal, an explicit operand, is given in the TimesRoman font.
3.0.4 Conventions for Instruction Names
Instructions in the Registers to Register Format (defined below) have names beginning with the word Register and mneumonics beginning with the letter R. Instructions in the Quick Register Format (also defined below) have names beginning with the Quick and mneumonics beginning with the letter Q. Instrucions that take all their operands from Stack have no adjectives in their instruction names.
Here are three of the instructions that perform addition:
1) RADD Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
Instruction Name: Register Add.
2) QADD Stack[S] ← Rs + Rb + Carry; Carry ← 0.
Name Instruction: Quick Add.
3) ADD Stack[S-1] ← Stack[S] + Stack[S-1] + Carry; Carry ← 0; S ← S — 1;
Instruction Name: Add.
3.1 Addition
ADDB
Stack[S] ←
Stack[S] + zExt[literal] + Carry; Carry ← 0.
Instruction Name: Add Byte.
Opcode: 10010100, 94.
Interpretation of Operands: Signed.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
ADDDB
Stack[S] ←
Stack[S] + zExt[literal] + Carry; Carry ← 0.
Instruction Name: Add Double byte.
Opcode: 11010100, D4.
Interpretation of operands: Signed.
Format: Literal Halfword (LH).
[Artwork node; type 'ArtworkInterpress on' to command tool]
ADD
Stack[S-1] ←
Stack[S] +
Stack[S-1] + Carry; Carry ← 0;
S ←
S — 1;
Instruction Name: Add.
Opcode: 01000100, 44.
Interpretation of Operands: Signed.
Format: Implicit (I).
RADD Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
Instruction Name: Register Add.
Opcode: 11000100, C4.
Interpretation of operands: Signed.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
QADD
Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
Name Instruction: Quick Add.
Opcode: 10000100, 84.
Interpretation of operands: Signed.
Format: Quick Register (QR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RUADD Rc ← Ra + Rb + Carry; Carry ← CarryOut.
Instruction Name: Register Unsigned Add.
Opcode: 11001110, CE.
Interpretation of operands: Unsigned.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RVADD Rc ← Ra + Rb.
Instruction Name: Register Vanilla Add.
Opcode: 11001100, CC.
Interpretation of Operands: Small Integer.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
3.2 Subtraction
SUBB
Stack[S] ←
Stack[S] — zExt[literal] — Carry. Carry ← 0.
Instruction Name: Subtract Byte.
Opcode: 10010101, 95.
Interpretation of operands: Signed.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
SUBDB
Stack[S] ←
Stack[S] — zExt[literal] — Carry; Carry ← 0.
Instruction Name: Subtract Double Byte.
Opcode: 11010101, D5.
Interpretation of operands: Signed.
Format: Literal Halfword (LH).
[Artwork node; type 'ArtworkInterpress on' to command tool]
SUB
Stack[S-1 ] ←
Stack[S-1 ] — Stack[S] — Carry. Carry ← 0;
S ←
S — 1.
Instruction Name: Substract.
Opcode: 01000101, 45.
Interpretation of operands: Signed
Format: Implicit (I).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RSUB Rc ← Ra — Rb — Carry. Carry ← 0.
;
S ←
S
— 1.
Instruction Name: Register Subtract.
Opcode: 11000101, C5.
Interpretation of operands: Signed.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
QSUB Rc ← Ra — Rb — Carry; Carry ← 0; trap on overflow.
Instruction Name: Quick Subtract.
Opcode: 10000101, 85.
Interpretation of operands: Signed.
Format: Quick Register (QR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RUSUB Rc ← Ra — Rb — Carry; Carry ← ~ CarryOut
Instruction Name: Register Unsigned Subtract.
Opcode: 11001111, CF.
Interpretation of operands: Unsigned.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RVSUB Rc ← Ra — Rb.
Instruction Name: Register Vanilla Subtract.
Opcode: 11001101, CD.
Interpretaion of Operands: Small Integer.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
3.3 Logical Operations
AND
Stack[S-1] ←
Stack[S]
AND
Stack[S-1];
S ←
S — 1;
Instruction Name: AND.
Opcode: 01000001, 41.
Format: Implicit (I).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RAND Rc ← Ra AND Rb.
Instruction Name: Register AND.
Opcode: 11000001, C1.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
QAND
Rc ← Ra AND Rb.
Instruction Name: Quick AND.
Opcode: 10000001, 81.
Format: Quick Register (QR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
OR
Stack[S-1] ←
Stack[S] OR
Stack[S-1];
S ←
S — 1.
Instruction Name: OR.
Opcode: 01000000, 40.
Format: Implicit (I).
[Artwork node; type 'ArtworkInterpress on' to command tool]
ROR Rc ← Ra OR Rb.
Instruction Name: Register OR.
Opcode: 11000000, C0.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
QOR Rc ← Ra OR Rb.
Instruction Name: Quick OR.
Opcode: 10000000, 80.
Format: Quick Register (QR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RXOR Rc ← Ra XOR Rb.
Instruction Name: Register XOR.
Opcode: 11001000, C8.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
3.4 Loads
The word load is used in an instruction name if the instruction pushes something onto the EU stack. The word read is used in the instruction name if the instruction retrieves something from memory. (c.f. Store/write, section 3.5)
LIB
Stack[S+1] ← zExt[literal];
S ←
S + 1.
Instruction Name: Load Immediate Byte.
Opcode: 10010010, 92.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
LIDB
Stack[S+1] ← zExt[literal];
S ←
S + 1.
Instruction Name: Load Immediate Double Byte.
Opcode: 11010010, D2.
Format: Literal Halfword (LH).
[Artwork node; type 'ArtworkInterpress on' to command tool]
LIQB
Stack[S+1] ← zExt[literal];
S ←
S + 1.
Instruction Name: Load Immediate Quad Byte.
Opcode: 00110010, 32.
Format: Literal Word (LW).
[Artwork node; type 'ArtworkInterpress on' to command tool]
LRn
Stack[S+1] ← Locals[n];
S ←
S + 1. n IN[0..16)..
Instruction Name: Load Register n.
Opcodes: 01100000 — 01101111, 60 — 6F.
Format: Locals Register (LR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
LCm
Stack[S+1] ← Constants[m];
S ←
S + 1. m IN[0..8).
Instruction Name: Load Constant m.
Opcodes: 00010000 - 00010111, 10 - 17 (8 instructions).
Format: Implicit (I).
[Artwork node; type 'ArtworkInterpress on' to command tool]
LRIn
Stack[S+1] ← Mem[Locals[n] + zExt[offset]];
S ←
S + 1. n IN[0..16)..
Instruction Name: Load Register Indexed n.
Opcodes: 10100000 — 10101111, A0 - AF.
Format: Index Register Offset (XO).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RB
Stack[S] ← Mem[
Stack[S] + zExt[literal]]).
Instruction Name: Read using byte offset.
Opcode: 10011000, 98.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
QRX
Rc ← Mem[Ra + Rb].
Instruction Name: Quick Read indeXed.
Opcode: 10000010, 82.
Format: Quick Register (QR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Note: This is a short form of RRX.
RSB
Stack[S+1] ← Mem[
Stack[S] + zExt[literal]];
S ←
S + 1.
Instruction Name: Read Save using Byte offset.
Opcode: 10011010, 9A.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool] I
RRX Rc ← Mem[Ra + Rb].
Instruction Name: Register Read indeXed.
Opcode: 11000010, C2.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RX
Stack[S-1] ← Mem[
Stack[S-1] +
Stack[S]];
S ←
S — 1.
Instruction Name: Read indeXed.
Opcode: 01000010, 42.
Format: Implicit (I).
[Artwork node; type 'ArtworkInterpress on' to command tool]
LGF
Stack[S+1] ← Mem[
Aux[0] + zExt[literal]];
S ←
S + 1.
Instruction Name: Load Global Frame.
Opcode: 11010000, D0.
Format: Operand Double Byte.
[Artwork node; type 'ArtworkInterpress on' to command tool]
Note: This instruction may be used to load the global frame pointer from the global frame table into a Stack register. In general, the LIQB instruction is faster than the LGF instruction because it loads the global frame pointer from the instruction stream, not from memory.
RRI Locals[regA] ← Memory[Locals[regB] + zExt[offset]].
Instruction Name: Read Register Indexed.
Opcode: 11011010, DA.
Format: Index—Register Register—Offset (XRO).
[Artwork node; type 'ArtworkInterpress on' to command tool]
RAI Locals[regA] ← Mem[Aux[regB] + zExt[offset]].
Instruction Name: Read Auxiliary register Indexed.
Opcode: 11011000, D8.
Format: Index—Register Register—Offset (XRO).
[Artwork node; type 'ArtworkInterpress on' to command tool]
LIP
Stack[S+1] ← ProcReg[literal];
S ←
S + 1.
Instruction Name: Load from Internal Processor register.
Opcode: 10010000, 90.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Notes:
1) ProcReg is an abbreviation for Processor Registers. It is an enumerated type of 256 registers that includes all registers which can be accessed using LIP and SIP (Store to Internal Processor register) instructions. For a complete listing of the accessible registers contained in ProcReg see Chapter 2.0.
2) LIP[EldestPC] is illegal in user mode.
3) LIP requires 1 cycle on any EU register and 5 cycles on any IFU register. The extra cycles on IFU registers are required to ensure that instructions immediately before the LIP do not modify the register that LIP is reading.
4) The Field register read by LIP is a shadow copy of the collection of gates which actually control the field unit; the shadow copy exists to facilitate saving and restoring the state of the field unit on a process switch. The shadow register is loaded whenever the Field register is loaded by either SIP or FSDB.
5) A LIP to an undefined register number, [160..239] or [246..255], will cause no harmful effect and manipulate the stack in the normal way; the value pushed is undefined. Register numbers in the range [0..239] have the same timing as a legal EU LIP; [240..255] have the same timing as a legal IFU LIP.
3.5 Stores
In general, the word store is used in an instruction name if the instruction moves data from Stack to an EU register ( Locals[], Constants[] or AuxRegs[]). The word write is used if the instruction moves data from Stack to Memory. Put Swapped is used for instructions that take a pointer and value from Stack, write the value to Memory at a small offset from the pointer, pop the value from the Stack, and leave the pointer on Stack. (The SRI instruction does not follow these conventions.)
EXDIS
Stack[S—1] ←
Stack[S];
S ←
S — 1.
Instruction Name: EXchange DIScard.
Opcode: 01001011, 4B.
Format: Implicit (I).
[Artwork node; type 'ArtworkInterpress on' to command tool]
DUP Stack[S+1] ← Stack[S]; S ← S + 1.
Instruction Name: Duplicate.
Opcode: 01001000, 48.
Format: Implicit (I).
SRn Locals[n] ←
Stack[S];
S ←
S — 1. n IN[0..16).
Instruction Name: Store Register n.
Opcodes: 01110000 — 01111111, 70 - 7F.
Format: Locals Register (LR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
WB Mem[
Stack[S] + zExt[literal]] ←
Stack[S—1];
S ←
S — 2.
Instruction Name: Write using Byte offset.
Opcode: 10011001, 99.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
WSB Mem[
Stack[S—1] + zExt[literal]] ←
Stack[S];
S ←
S — 2.
Instruction Name: Write Swapped using Byte offset.
Opcode: 10011011, 9B.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
PSB Mem[
Stack[S—1] + zExt[literal]] ←
Stack[S];
S ←
S — 1.
Instruction Name: Put Swapped using Byte offset.
Opcode: 10011111, 9F.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
SRIn Mem[Locals[n] + zExt[offset]] ← Stack[S];
S ←
S — 1. n IN[0..16)..
Instruction Name: Store Register Indexed n.
Opcodes: 10110000 — 10111111, B0 - BF.
Format: Index Register Offset (XO).
[Artwork node; type 'ArtworkInterpress on' to command tool]
SIP ProcReg[literal] ←
Stack[S];
Instruction Name: Store to Internal Processor register.
Opcode: 10010001, 91.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Notes:
SIP is the most efficient way to store into AuxRegs or Constants. See the table in Chapter 2.0 for the interpretation of the literal byte as a register number.
1) SIP is illegal in user mode.
2) SIP requires 1 cycle on any EU register, 5 cycles on any IFU register; the extra cycles on IFU registers ensure that the immediately following instructions do not use the register which SIP is modifying and that no K bus conflict occurs when SIP sends its data from the EU back to the IFU.
3) Any SIP to an undefined register number, [160..239] or [246..255], will cause no harmful effect and manipulate the stack in the normal way; 128 (Spare) may also be an undefined register; SIP[ToKbus] may interfere with K bus use by following instructions.
WRI Mem[Locals[regB] + zExt[offset]] ← Locals[regA].
Instruction Name: Write Register Indexed.
Opcode: 11011011, DB.
Format: Index—Register Register—Offset (XRO).
[Artwork node; type 'ArtworkInterpress on' to command tool]
WAI Mem[Aux[regB] + zExt[offset]] ← Locals[regA].
Instruction Name: Write Auxilliary register Indexed.
Opcode: 11011001, D9.
Format: Index—Register Register—Offset (XRO).
[Artwork node; type 'ArtworkInterpress on' to command tool]
CST (
Stack[S+1] ← Mem[
Stack[S-2] + zExt[literal]]; If
Stack[S+1] =
Stack[S] then Mem[
Stack[S-2] + zExt[literal]] ←
Stack[S-1];
S ←
S + 1.)
Instruction Name: Conditional Store.
Opcode: 10001100, 8C.
Format: Literal Byte (LB).
[Artwork node; type 'ArtworkInterpress on' to command tool] I
Note: The Conditional Store Instruction is used as an atomic test and set of shared data. If a processor wants to perform an atomic conditional store, it executes the CST instruction which performs a read/hold of the memory location specified (Mem[Stack[S-2] + zExt[literal]]). The hold reserves the memory bus for this CST instruction and prevents any other memory operation from executing. If the contents of that memory location equals an expected value (from Stack[S]), the store is performed and the bus is released. If there is not agreement, the data is not stored, the bus is released. The mechanism by which the instruction releases the memory bus in the case where the write is not performed is to do a normal read (without hold) of the test location. In either case, the result of the initial read is pushed onto the top of the stack. This instruction can be expressed by the following CEDAR program DragonMemoryOpsImpl given below.
Here are definitions used in the implementation:
DragonMemoryOps:
CEDAR
DEFINITIONS = {
FetchIndirect: PROCEDURE [pointer: DragonTooth.Address, offset: DragonTooth.Word] RETURNS [value: DragonTooth.Word];
FetchIndirectHold:
PROCEDURE [pointer: DragonTooth.Address, offset: DragonTooth.Word]
RETURNS [value: DragonTooth.Word];
Just like FetchIndirect except that the next memory operation belongs to this processor.
Release:
PROCEDURE []
RETURNS [];
a memory operation that just releases the hold placed by a call of FetchIndirectHold.
StoreIndirect: PROCEDURE [pointer: DragonTooth.Address, offset: DragonTooth.Word, value: DragonTooth.Word] RETURNS [];
CStore:
PROCEDURE
[
pointer: DragonTooth.Address,
offset: DragonTooth.Word,
new: DragonTooth.Word,
old: DragonTooth.Word
]
RETURNS [
afterPointer: DragonTooth.Address,
afterNew: DragonTooth.Word,
afterOld: DragonTooth.Word,
sample: DragonTooth.Word
];
}.
Here is the implementation:
DIRECTORY
DragonMemoryOps,
DragonTooth;
DragonMemoryOpsImpl:
CEDAR
PROGRAM = {
CStore:
PROCEDURE
[
pointer: DragonTooth.Address,
offset: DragonTooth.Word,
new: DragonTooth.Word,
old: DragonTooth.Word
]
RETURNS [
afterPointer: DragonTooth.Address,
afterNew: DragonTooth.Word,
afterOld: DragonTooth.Word,
sample: DragonTooth.Word
] = {
This is really an instruction, not a procedure call, so it doesn't really take 4 parameters and return 5 results, it just leaves the parameters on the stack and pushes the sample.
sample ← FetchIndirectHold[pointer: pointer, offset: offset];
note that this reads sample, but no one can change it until after one of the stores below.
Note that this means that the fetches of sample, old, pointer, offset, and new had better not be fetches from memory (i.e. they must be in registers), since the next memory operation releases the hold.
IF sample = old
THEN
StoreIndirect[pointer: pointer, offset: offset, value: new]
};
}.
3.6 Input/Output Operations
Input/output or IO instructions are generalized memory references that use the P bus to control coproccessors (the floating point unit, the Lisp interpreter, and bitBlt processor), the memory system including its caches, and possibly other devices. It is possible to execute any ordinary read or write using the IOS instruction.
An IO instruction can set up or bits to tell control to pass from the IFU to the Lisp interpreter so the the EU becomes the slave of the the Lisp interpreter instead of the IFU. Also the IO can issue commands over the M bus to give bitBlt, not the IFU control.
The second byte following the opcode of an IO instruction designates a device number. The three low-order bits of this byte also control user mode traps, kernel address checking and the function of the instruction (read or write) as follows:
4B 1 = Illegal in user mode.
2B 1 = Perform kernel address check.
1B 0 = PRead, 1 = PWrite.
It is expected that these user and address check controls will be specified in one of three ways:
1xx Illegal in user mode (map or cache control operations, for example).
011 A PWrite which writes storage and is legal in user mode
(but must not write into the Kernel).
00x a PRead or PWrite which sends information to a coprocessor, such as the
floating point unit, without modifying storage.
Here is how these operations might be used to control a floating point coprocessor to perform the FADD (Floating point add) function. Three instructions must be executed to do this. The first instruction might "enter" one word of data in the floating point unit and use the address ...
IOL
SELECT TRUE FROM
IsRead[DeviceNo] => Stack[S+1] ← PRead[PBusAddr+[S], DeviceNo, Stack[S-1]];
S ←
S + 1;
IsWrite[DeviceNo] => PWrite[PBusAddr, DeviceNo, Stack[S]];
S ←
S — 1;
ENDCASE;
Instruction Name:
Opcode: 11011101, DD.
Format:
[Artwork node; type 'ArtworkInterpress on' to command tool]
ION
SELECT TRUE FROM
IsRead[DeviceNo] => Stack[S+1] ← PRead[PBusAddr, DeviceNo];
IsWrite[DeviceNo] => PWrite[PBusAddr, DeviceNo, Stack[S]];
ENDCASE;
Instruction Name:
Opcode: 11011110, DE.
Format:
[Artwork node; type 'ArtworkInterpress on' to command tool]
IOS
SELECT TRUE FROM
IsRead[BetaZ] => Stack[S] ← PRead[PBusAddr+Stack[S], BetaZ];
IsWrite[BetaZ] => PWrite[PBusAddr+[S], BetaZ, Stack[S-1]];
S ←
S — 2;
ENDCASE; ??is the
S ←
S — 2 only executed in the write case??
Instruction Name:
Opcode: 11011100, DC.
Format:
[Artwork node; type 'ArtworkInterpress on' to command tool]
3.7 Field Unit Operations
See Chapter 2.4 for a complete explanation of the Field Unit.
FSDB FieldDescriptor ←
Stack[S] + literal.
S ←
S — 1.
Instruction Name: Field Setup Double Byte.
Opcode: 11111100, FB.
Format: Literal Halfword (LH).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Note: This instruction is equivalent to (but smaller and faster than) the two instructions, Add Double Byte (ADDDB) and Store to Internal Processor register (SIP).
RFU Rc ← Field
Unit.Operate[Ra, Rb, FieldDescriptor]
Instruction Name: Register Field Unit.
Opcode: 11001010, CA.
Format: Registers to Register (RRR).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Note: This a general shift operation, including extract, insert, and shift. The Field register supplies the field descriptor.
SHL
Stack[S] ← Field
Unit.Operate[
Stack[S],
0, literal].
Instruction Name: Shift Left.
Opcode: 11111000, F8.
Format: Literal Halfword (LH).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Note: This operation shifts and masks a single word. This single word is passed to Procedure FieldUnit.Operate asASL the Left argument. The Right argument to Procedure FieldUnit.Operate is zero. The 16-bit constant contained in literal determines the action taken. (SHL does not use or affect the Field register.) This instruction is particularly useful for left shifting, all or some right justified portion of a word.
Example:
Left Shift - If (FD.insert = false & FD.mask = 32) then FD.shift = the number of bits the original input word will be left-shifted. (Zeros are inserted on right end.)
SHR
Stack[S] ← Field
Unit.Operate[
Stack[S],
Stack[S], literal].
Instruction Name: Shift Right.
Opcode: 11111001, F9.
Format: Literal Halfword (LH).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Note: This operation shifts and masks a single word. This single word, Stack[S], is passed to Procedure FieldUnit.Operate as both the Left and Right arguments. The 16-bit constant contained in literal determines the action taken. (SHR does not user or affect the Field register.) It is particularly useful for shifting right, rotating words, and extracting fields.
Examples:
Right Shift - If (fieldOp.insert = false & fieldOp.shift= fieldOp.width) then 32 - fieldOp.shift = the number of bits the original input word will be right-shifted.
Rotate - If (fieldOp.insert = false & fieldOp.width = 32) then 32 - fieldOp.shift = the number of bits to right rotate from the original input.
Extract - If ( fieldOp.insert = false & fieldOp.shift >= fieldOp.width) then the final output will contain a right- justified field of length fieldOp.width extracted from the operand at bit (fieldOp.shift - 1).
SHD
Stack[S-1] ← Field
Unit.Operate[
Stack[S-1],
Stack[S], literal];
S ←
S — 1.
Instruction Name: Shift Double.
Opcode: 11111010, FA.
Format: Literal Halfword (LH).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Note: This operation shifts and masks double words. The two words, Stack[S-1] and Stack[S] are passed to Procedure FieldUnit.Operate as the Left and Right arguments, respectively. The 16-bit constant contained in literal determines the action taken. (SHD does not use or affect the Field register.) It is especially useful for extracting arbitrary fields from a pair of words, or inserting fields.
Examples:
Extract - If ( FD.insert = false & FD.shift > FD.mask) then the final output will contain field of length FD.mask inserted into array of 32 zero's at bit position (32 -Fd.shift).
Insert - If (fieldOp.insert = true & fieldOp.width > fieldOp.shift then the final ouput will contain a field of length (fieldOp.width - fieldOp.shift) extracted from the original word beginning at bit position fieldOp.Shift + (32 - fieldOp.width) and inserted into the original input word at bit position (32 - fieldOp.shift).
3.8 The IFU Indices — S and L
The S and L indices are numbers in the range [0..127]. The literal values added to these indices are also in the range [0..127]. Future versions of Dragon may double the size of the S and L indices, making S, L and the literal values used to increment them unsigned 8-bit quantities.
DIS
S ←
S — 1.
Instruction Name: Discard.
Opcode: 01001001, 49.
Format: Implicit (I).
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Note: DIS is a frequently used short form for AS 127.
AL
L ←
L + literal.
Instruction Name: Add to L.
Opcode: 10001001, 89.
Interpretation of operands: Small Integer.
Format: Literal Byte (LB).
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Note: Used primarily for saving and restoring stack frames.
ALS
L ←
S + literal.
Instruction Name: Add to L from Stack.
Opcode: 10001000, 88.
Interpretation of operands: Small Integer.
Format: Literal Byte (LB).
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Note: Used at procedure entry to establish the base register index of the local frame.
AS
S ←
S + literal.
Instruction Name: Add to Stack.
Opcode: 10001011, 8B.
Interpretation of operands: Small Integer.
Format: Literal Byte (LB).
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Note: EU Stack overflow occurs when an instruction puts S in the range [SLimit..Slimit+16). If the literal argument for AS should not be larger than 15; if it is, it may invalidate the test for EU Stack overflow. (A literal argument of 16 would detect EU Stack overflow, but would not leave an extra word necessary to push the IFUStatus.)
ASL
S ←
L + literal.
Instruction Name: Add to Stack from L.
Opcode: 10001010, 8A.
Interpretation of operands: Small Integer.
Format: Literal Byte (LB).
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Note: See note for AS.
3.9 - 3.11 Transfers of Control
In the following three sections the PC on the left-hand side of the assignment statement is always the PC for the next instruction. In other words, nextPC ← PC + some expression.
3.9 No Operation (NoOps)
NoOps look like short jumps except that they do not clear the pre-fetch buffer in the IFU.
J1
PC ←
PC + 1.
Instruction Name: Jump One (1).
Opcode: 01010110, 56.
Format: Implicit (I).
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J2
PC ←
PC + 2.
Instruction Name: Jump Two (2).
Opcode: 10010110, 96.
Format: Literal Byte (LB).
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J3
PC ←
PC + 3.
Instruction Name: Jump Three (3).
Opcode: 11010110, D6.
Format: Literal Halfword (LH).
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J5
PC ←
PC + 5.
Instruction Name: Jump Five (5).
Opcode: 00110110, 36.
Format: Literal Word (LW).
3.10 Unconditional Jumps
JB
PC ←
PC + sExt[literal].
Instruction Name: Jump using Byte offset.
Opcode: 10010111, 97.
Format: Literal Byte (LB).
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JDB
PC ←
PC + sExt[literal].
Instruction Name: Jump using Double Byte offset.
Opcode: 11010111, D7.
Format: Literal Halfword (LH).
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JQB
PC ← literal.
Instruction Name: Jump using Quad Byte offset.
Opcode: 00110111, 37.
Format: Literal Word (LW).
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Note: This instruction is useful in trap vectors and other long transfers.
SJ
PC ←
PC + Stack[S];
S ←
S — 1.
Instruction Name: Stack Jump.
Opcode: 01010111, 57.
Format: Implicit (I).
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3.11 Conditional Jumps
The conditional jump instructions are defined in pairs. One instruction of each pair predicts that the jump should be taken; its mneumonic includes a trailing lowercase j. The other instruction of the pair predicts that the jump should not be taken and does not include the trailing j.
RJEBj If Rs = Rb then
PC ←
PC + sExt[displacement]. Jump predicted.
Instruction Name: Register Jump Equal Byte.
Opcode: 11101101, ED.
Format: Register Displacement (RD).
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RJEB If Rs = Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Equal Byte. Jump not predicted.
Opcode: 11100001, E1.
Format: Register Displacement (RD).
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JEBBj If
Stack[S] = zExt[literal] then
PC ←
PC + sExt[displacement];
S ←
S — 1.
Instruction Name: Jump Equal Byte Byte. Jump predicted.
Opcode: 11110010, F2.
Format: Literal Byte Displacement (LBD).
4 [Artwork node; type 'ArtworkInterpress on' to command tool]
JEBB If
Stack[S] = zExt[literal] then
PC ←
PC + sExt[displacement];
S ←
S — 1.
Instruction Name: Jump Equal Byte Byte. Jump not predicted.
Opcode: 11110000, F0.
Format: Literal Byte Displacement (LBD).
4 [Artwork node; type 'ArtworkInterpress on' to command tool]
JNEBBj If
Stack[S] ~= zExt[literal], then
PC ←
PC + sExt[displacement];
S ←
S — 1.
Instruction Name: Jump Not Equal Byte Byte. Jump predicted.
Opcode: 11110011, F3.
Format: Literal Byte Displacement (LBD).
4 [Artwork node; type 'ArtworkInterpress on' to command tool]
JNEBB If
Stack[S] ~= zExt[literal], then
PC ←
PC + sExt[displacement];
S ←
S — 1.
Instruction Name: Jump Not Equal Byte Byte. Jump not predicted.
Opcode: 11110001, F1.
Format: Literal Byte Displacement (LBD).
4 [Artwork node; type 'ArtworkInterpress on' to command tool]
RJNEBj If Rs ~= Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Not Equal Byte. Jump predicted.
Opcode: 11101001, E9.
Format: Register Displacement (RD).
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RJNEB If Rs ~= Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Not Equal Byte. Jump not predicted.
Opcode: 11100101, E5.
Format: Register Displacement (RD).
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RJGBj If Rs > Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Greater Byte. Jump predicted.
Opcode: 11101011, EB.
Format: Register Displacement (RD).
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RJGB If Rs> Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Greater Byte. Jump not predicted.
Opcode: 11100111, E7.
Format: Register Displacement (RD).
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RJGEBj If Rs >= Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Greater Equal Byte. Jump predicted.
Opcode: 11101010, EA.
Format: Register Displacement (RD).
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RJGEB If Rs >= Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Greater Equal Byte. Jump not predicted.
Opcode: 11100110, E6.
Format: Register Displacement (RD).
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RJLBj If Rs < Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Less Byte. Jump predicted.
Opcode: 11101110, EE.
Format: Register Displacement (RD).
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RJLB If Rs < Rb then
PC ←
PC + sExt[displacement]
Instruction Name: Register Jump Less Byte. Jump not predicted.
Opcode: 11100010, E2.
Format: Register Displacement (RD).
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RJLEBj If Rs <= Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Less Equal Byte. Jump predicted.
Opcode: 11101111, EF.
Format: Register Displacement (RD).
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RJLEB If Rs <= Rb then
PC ←
PC + sExt[displacement].
Instruction Name: Register Jump Less Equal Byte. Jump not predicted.
Opcode: 11100011, E3.
Format: Register Displacement (RD).
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3.12 Bounds Checks
The following instructions interpret their operands as 32-bit unsigned quantities. These instructions are used to check indexes against bounds and when a number is narrowed to fit into a subrange. In using the instructions for bounds-checking, the original range a <= num < b is first reduced to 0 <= num - a < b - a; after this reduction, unsigned arithmetic is appropriate for determining whether num - a is within the desired range. The hardware checks for number >= bound by trapping iff bound - number - 1 doesn't produce carry-out = 1.
RBC If (Ra < Rb ) then Rc ← Ra else trap.
Instruction Name: Register Bounds Check.
Opcode: 11000011, C3.
Interpretation of Operands: Unsigned.
Format: Registers to Register (RRR).
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BC If
NOT[Stack[S-1] < Stack[S]] then trap;
S ←
S — 1.
Instruction Name: Bounds Check.
Opcode: 01000011, 43.
Interpretation of Operands: Unsigned.
Format: Implicit (I).
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Note: BC is a short form of RBC that may be used when testing values that are from the stack.
QBC If (Ra < Rb ) then Rc ← Ra else trap.
Instruction Name: Quick Bounds Check.
Opcode: 10000011, 83.
Interpretation of Operands: Unsigned.
Format: Quick Register (QR).
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Note: This is a short form of RBC.
3.13 Procedure Calls and Returns
When a procedure is called, the current PC and L are saved in the IFU Stack:
SaveState:
PROCEDURE [PC, L]
RETURNS [] = {
Youngest ← Youngest + 1;
handleOverflow;
IFUStack[youngest] ← [PC, L];
};
When the overflow trap is taken, the IFU Stack contains 12 entries.
Upon return, PC and L are assigned youngest values from the IFUStack:
ReturnState:
PROCEDURE []
RETURNS [PC, L] = {
[PC, L] ← IFUStack[youngest];
Youngest ← Youngest — 1;
};
LFC SaveState[
PC, L];
PC ←
PC + sExt[literal].
Instruction Name: Local Function Call.
Opcode: 11010001, D1.
Format: Literal Halfword (LH).
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DFC SaveState[
PC, L];
PC ← literal.
Instruction Name: Direct Function Call.
Opcode: 00110001, 31.
Format: Literal Word (LW).
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SFC SaveState[
PC, L];
PC ←
Stack[S];
S ←
S — 1.
Instruction Name: Stack Function Call.
Opcode: 01001100, 4C.
Format: Implicit (I).
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SFCI SaveState[
PC, L]; PC ← Mem[
Stack[S]].
Instruction Name: Stack Function Call Indirect.
Opcode: 01001101, 4D.
Format: Implicit (I).
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KFC SaveState[
PC, L];
Stack[S+1] ←
Status;
S ←
S + 1; Set kernel mode;
PC ← InstTrap[KFC].
Instruction Name: Kernel Function Call.
Opcode: 01010100, 54.
Format: Implicit (I).
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Note: This instruction is used by user (or kernel) mode code to call kernel operations.
RETN ReturnState[
PC, L];
Instruction Name: RETurn No adjustment to S.
Opcode: 01001110, 4E.
Format: Implicit (I).
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RET
S ←
L + literal; ReturnState[
PC, L];
Instruction Name: RETurn.
Opcode: 10001110, 8E.
Format: Literal Byte (LB).
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RETK
Status ←
Stack[S]; ReturnState[
PC, L + sExt[literal]];
Instruction Name: Return from Kernel. Illegal in user mode.
Opcode: 10001111, 8F.
Format: Literal Byte (LB).
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Note: This instruction is used by kernel mode for two purposes: (1) to return to user mode, and (2) to return from a reschedule trap while atomically enabling traps.
3.14 Lisp Instructions
LADD
Stack[S-1] ←
Stack[S-1] +
Stack[S]; Carry ← 0.
S ←
S — 1.
Instruction Name: Lisp ADD.
Opcode: 01000110, 46.
Interpretation of Operands: Lisp.
Format: Implicit (I).
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QLADD Rc ← Ra + Rb; Carry ← 0.
Instruction Name: Quick Lisp Add.
Opcode: 10000110, 86.
Interpretation of operands: Lisp.
Format: Quick Register (QR).
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Note: This is a short form of RLADD.
RLADD Rc ← Ra + Rb; Carry ← 0.
Instruction Name: Register Lisp ADD.
Opcode: 11000110, C6.
Interpretation of Operands: Lisp.
Format: Registers to Register (RRR).
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LSUB
Stack[S-1] ←
Stack[S-1] —
Stack[S]; Carry ← 0.
S ←
S — 1.
Instruction Name: Lisp SUBtract.
Opcode: 01000111, 47.
Interpretation of Operands: Lisp.
Format: Implicit (I).
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Note: This is a short form of QLSUB and RLSUB.
QLSUB
Rc ← Ra — Rb. Carry ← 0.
Instruction Name: Quick Lisp SUBtract.
Opcode: 10000111, 87.
Interpretation of Operands: Lisp.
Format: Quick Register (QR).
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Note: This is a short form of RLSUB.
RLSUB Rc ← Ra — Rb. Carry ← 0.
Instruction Name: Register Lisp SUBtract.
Opcode: 11000111, C7.
Interpretation of Operands: Lisp.
Format: Registers to Register (RRR).
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