[Indigo]<Dragon>Documentation>PBus>PBusSpecs.tioga!5

PBusSpecs.tioga

Last Edited by: Barth, December 6, 1984 5:29:01 pm PST

DRAGON P BUS SPECIFICATIONS

DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY

The Dragon P Bus

Description and Specifications

Release as [Indigo]<Dragon>Documentation>PBusSpecs.tioga

Abstract: This memo describes the Dragon P bus. It is intended to be used both as a convenient source for information about the P bus and as a reference manual for bus specifications.

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

For Internal Xerox Use Only

Contents

1. Introduction

2. Bus Signals

3. Bus Operation

4. Bus Timing

1. Introduction

The P bus is a low latency synchronous bus that is used for local interconnection within a Dragon module (Figure 1). One P bus connects the prefetch buffer of a Dragon instruction fetch unit to a set of instruction caches. Another P bus connects the execution unit to a set of data caches and other devices local to a module such as a floating point accelerator.

There are approximately 42 wires on the P bus. The multiplexed data/address path, which is checked by a single parity bit, is 32 bits wide. Four additional wires define the bus command, which encodes the action during the current bus cycle (a bus cycle is defined in the same way as a processor cycle: namely, one complete period of the system-wide two-phase clock; these two phases are labeled A and B, by convention). Another set of three wires define the bus fault state which is the response from the addressed slave to the master. Addresses on the P bus are virtual as opposed to real, and the unit of addressing is the 32 bit word. A reject wire indicates that a slave is not yet ready to complete a command that was issued by the bus master. Finally an error wire is used to indicate that some component in the module has detected an unrecoverable error.

Within a Dragon module only one component is ever bus master on either P bus. This component is the instruction fetch unit.

The commands on the P bus consist of commands to caches and to the floating point accelerator. The cache commands are subdivided into an orthogonal set of 8. One bit of the command selects the address space to which the address bits apply. This may be I/O or memory. Another bit determines whether the operation is a fetch or a store. The last bit indicates whether the command is to lock the M bus so that a sequence of P bus commands can be considered atomic with respect to the memory or I/O state. The floating point commands allow data to be stored into and fetched from the floating point accelerator chips.

The remainder of this document goes into greater detail about the structure, operation, and timing of the P bus. The next section lists the bus signals in detail and gives the meaning of each signal. Section 3 next uses these signal definitions to explain how the bus operates by discussing how each of the commands causes information to flow within the system. Section 4 provides detailed timing diagrams for the bus.

2. Bus Signals

The P bus has 42 signal lines that are listed below, together with the meaning of each group of lines. The description uses the following naming conventions: S[a..b) denotes a group of b-a lines that encode the bits representing the signal S; most significant bits of the signal are written leftmost. A signal represented by a single wire is written unencumbered with the [) notation. All signals are assumed to follow positive logic unless they have an "n" at the beginning of the signal name. Finally, the letter "A" is appended to signal S if it is computed and becomes valid during phase A. Similiarly for "B". Encodings are given as decimal numbers in brackets after the associated mnemonics. The actual setup time at which the bus becomes valid prior to the falling edge of the appropriate clock has not yet been determined. The setup time of the address from the processor to the cache is approximately 40ns. The setup time of the data back to the processor from the cache is approximately 10ns.

PCmdA[0..4)

These four lines encode the P bus command. The P bus command specifies the action in progress during the current bus cycle; it is always asserted by the bus master. The commands currently defined are discussed later in Section 3.

PData[0..32)

The interpretation of these 32 lines depends on PCmdA[0..4) and the phase of the clock. During phase A of cache commands the PData lines represent the 32-bit address of an I/O or memory location; during phase B these lines contain the data being fetched or stored. For other commands the interpretation is more complicated. The detailed interpretation appears in Section 3.

PParityB

This line carries the parity bit for PData[0..32). The parity computed is odd and is valid only when data is being transmitted to or from a cache.

PRejectB

This line is used by a slave to indicate that it has not yet performed the command requested by the bus master. This line is driven low during phase A by every cache on the bus in order to remove the value established during phase B of the previous cycle.

When there are multiple caches on a P bus they must be configured so that one and only one cache responds to every address that can be issued by the processor. This eliminates the possibility of the processor issuing an address and no cache responding to the request. It also eliminates the possibility of several caches trying to drive the P bus at the same time.

The caches deassert PRejectB and PFaultB during every phase A because the processor then does not have decide if these lines are valid in any particular cycle in order to interpret them. Since there is no mechanism to arbitrate which cache controls these lines during idle cycles it is easiest to simply have them all drive this line inactive every cycle. Note that this mechanism requires that the value driven onto these lines during phase A remain stable through the following phase B even though they are not driven during phase B.

PFaultB[0..3)

These lines are used to indicate to the bus master that the operation it requested cannot be performed. The master must invoke a software routine that can interpret the code returned on these lines. The codes currently defined include None{0}, PageFault{1}, WriteProtectFault{2}, and FPFault{3}. These lines are driven low, just as PRejectB is, during phase A by every cache on the bus.

nPError

This line is used to signal a bus error. The only bus error currently defined is parity error. Note that this signal is asserted when low. Normally, a pullup resistor ensures it is not asserted.

3. Bus Operation

P bus operation is simply a sequence of commands, one per cycle. A command can take more than one cycle to complete if the slave indicates that it has not completed the requested operation, but no other command is allowed to start during this period.

The description below first takes up the floating point commands. It then describes the various cache commands. The detailed timing of each of the commands is not taken up here but is left to Section 4. Note that the value NoOp{0} is reserved to mean no operation and that the values Reserve1{1}, Reserve3{3}, Reserve6{6}, and Reserve7{7} are not yet defined and are reserved for future use.

3.1 Floating Point Commands

general mumble

FetchFPAlu {2}

Mumble, mumble

FetchFPMult {4}

Mumble, mumble

StoreFP {5}

Mumble, mumble

3.2 Cache Commands

The memory system, in which the cache is only one of many components, guarantees that every sequence of fetches or stores will be ordered so that at any point in time a fetch from the memory system over any P bus will retrieve the same value. It does not guarantee that stores will be completed in any deterministic order unless the hold bit (described below) is set.

The cache commands can most easily be described by independently discussing the semantics of each of the low order three bits in the command encoding. For the sake of completeness the mnemonics and encodings of each command are: Fetch{8}, Store{9}, FetchHold{10}, StoreHold{11}, IOFetch{12}, IOStore{13}, IOFetchHold{14}, IOStoreHold{15}.

All of these commands transmit a 32 bit address from the processor to the caches during phase A. If the command is a store then the processor sends 32 bits of data plus parity to the caches during the next phase B regardless of the state of the PRejectB or PFaultB lines. If the command is a fetch then some cache returns 32 bits of data plus parity to the processor during the next phase B, assuming that no reject or fault has occurred. If a cache cannot immediately complete the command requested during phase A then it asserts PRejectB during every phase B until the cycle during which the command is completed or the cache has determined that it can never complete the command. If the command is completed then PRejectB is deasserted and, if the command was a fetch, the addressed location's data is driven onto the bus. If the command cannot be completed then on the last cycle during which the cache asserts PRejectB it also asserts a nonzero fault code on PFaultB.

Fetch/Store

This bit indicates whether the command is to be a transfer from processor to memory (store) or memory to processor (fetch). A zero on this line indicates fetch while a one indicates store. It is the low order bit of the encoding, bit 3.

Hold

This bit indicates that this command starts or continues a sequence of operations that are atomic with respect to the I/O and memory state space. Any command on the P bus other than NoOp or a cache command with this bit set, terminates the atomic sequence. If the cache sends a nonzero fault code to the processor it also terminates the atomic sequence. A one bit here indicates hold while a zero indicates do not hold. This bit is bit 2, the next to lowest order bit of the encoding.

IO/Memory

This bit determines which address space the command is taking place within. A zero indicates memory space while a one indicates I/O space. It is bit 1, the next to highest order bit of the encoding.

If the cache detects an unrecoverable error, such as a parity error in its internal RAM, then it pulls nPError low.

4. Bus Timing

This section gives the detailed timing of each bus command. In the timing diagrams used below, each row corresponds to one phase of the clock. Each pair of rows corresponds to one cycle. Actions during each phase are indicated using Mesa like statements. Wait cycles are indicated by a vertical bar next to a pair of phases. The variable w will be used to represent the number of wait cycles.

Detailed timing is given for only one fetch and one store command since the timing is identical for the other 3 fetch and 3 store commands.

Only the requirements are shown in the diagrams. The value of a wire or bus is undefined during phases that the value is not explicitly given with the exception of nPError which is assumed to always be high.

4.1 FetchFPAlu

Mumble, mumble

4.2 FetchFPMult

Mumble, mumble

4.3 StoreFP

Mumble, mumble

4.4 Fetch

The three significant cases of fetch timing are shown in Figure 2. It is not possible for the cache to issue a fault without a reject. During the first phase A the processor sends the fetch command and the 32 bit address to all of the caches and all of the caches deassert reject and fault. If the addressed datum is in the addressed cache (Figure 2a) then during the first phase B the cache drives PRejectB false, PFaultB to no fault, PData to the datum, and PParityB to the odd parity of the datum. If the datum is not in the cache then the cache will drive PRejectB true during every phase B (the second B of Figures 2b and 2c) until the datum becomes available or the cache determines that the datum will never become available. During the first phase B after the datum becomes available (the third B of Figure 2b) the cache drives PRejectB false, PFaultB to no fault, PData to the datum, and PParityB to the odd parity of the datum. If the datum will never become available then the cache terminates the command by setting PRejectB true and setting PFaultB to something besides None.

4.5 Store

The three significant cases of store timing are shown in Figure 3. It is not possible for a cache to issue a fault during the same cycle that the store request was issued. During the first phase A the processor sends the store command and the 32 bit address to all of the caches and all of the caches deassert reject and fault. During the first phase B the processor sends the data with its parity. If the addressed location is in the addressed cache (Figure 3a) then during the first phase B the cache drives PRejectB false and PFaultB to no fault. If the addressed location is not in the addressed cache or the cache must determine whether a write is permitted to the addressed location then during the first phase B the cache sets PRejectB true and PFaultB to no fault (Figures 3b and 3c). Then the cache takes an arbitrary number of cycles to fetch the addressed location into the cache or determine whether the store is permitted. During these cycles all of the caches will set PRejectB to false and PFaultB to none during phase A and the addressed cache will set PRejectB to true and PFaultB to none during phase B. If the store is permitted then during the final cycle the addressed cache will set PRejectB to false and PFaultB to none during the final phase B of the command (Figure 3b). If the store is not permitted then the cache will set PRejectB to true and set PFaultB to something besides None (Figure 3c).

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