Dragon CMOS Design Rules
FOR INTERNAL XEROX USE ONLY
XEROX
Dragon CMOS Design Rules
Jeff Hoel
1.  Introduction
1.1.  Purpose
The purpose of this document is to specify a set of design rules for CMOS VLSI circuits which can be used by designers of Dragon (and other) chips to assure that they can be fabricated by multiple facilities.  So far, the facilities of interest are Xerox PARC's Integrated Circuits Laboratory (ICL) and VLSI Technology Inc. (VTI).
The intent is that theses rules will remain stable at least until the first generation of Dragon chips, fabricated with two-micron gates, is working.  The rules are consisent with projection alignment lithography, which is consistent with supporting an MPW (multi-project wafer) approach to fabrication.
1.2.  Revision History
Original: August 21, 1985.
Revision A:  October 11, 1985
Updates to reflect use of VTI's new rules [6]
Revision B:  (never formally released) ~ December 12, 1985
Minimum via size reduced to 2 x 2 lambda.
Larger surrounds for non-minimum-size cuts and vias.
Current limit rules added.
New N-well rules.
Brand new format!
And more.
Revision C:  January 26, 1986
Pro forma.
1.3.  References
1.3.1.  Old CMOS Design Rules
[2]  CMOS Lambda Layout Design Rules; Greg Spadea; VLSI Technology Inc.; Document Number 02-ECL-2, Rev *G, May 16, 1985.
1.3.2.  Two-Micron CMOS Design Rules
[1]  ICL CMOS III Design Rules, with Rationale; Richard Bruce and Ed McCreight; Xerox Internal Memo; /Cherry/VLSI/CMOSDesignRules.tioga, -.press, May 8, 1985.
[6]  CMOS Lambda Layout Design Rules for Advanced Lithography; Greg Spadea; VLSI Technology Inc.; Document Number 02-ECLA-2, Rev *B, July 29, 1985.
1.3.3.  Two-Micron CMOS Process Parameters
[3]  Report On Process and Electrical Parameters; Richard Bruce and John Chen; Xerox PARC; /Cherry/VLSI/CMOSParameters.bravo, -.press, March 5, 1985.
[4]  VTI Spice Models for the 2 Micron N-Well CMOS (C4) Process; Mike Misheloff; VLSI Technology Inc.; Document Number 16-00503, Rev *A, March 27, 1985.
1.3.4.  Sub-Two-Micron CMOS Design Rules
[5]  CMOS IV Preliminary Design Rules; Xerox ICL/MEC; unpublished.
1.3.5.  Design Rules In General
[7]  Meeting with Bill Oldham, July 12, 1985;
/Ivy/Hoel/Dragon/Foundry/OldhamMeeting12July85.tioga.
1.3.6.  Design Rule Summary
[8]  Summary of Dragon CMOS Design Rules; Jeff Hoel; Xerox internal document /Ivy/Hoel/Dragon/Foundry/DesignRuleSummary.tioga, October 11, 1985.
1.3.7.  Library of Standard Cells
[*]  **** [with pads we can all use]
1.3.8.  Other
[9]  The Design and Analysis of VLSI Circuits; Lance A. Glasser and Daniel W. Dobberpuhl; Addison-Wesley, Reading, MA, 1985.
[10]  <Latch-up Tests>; Alan Lewis; Xerox; to be published soon (as of December 1985).
1.4.  Format
We have decided, as of Revision B, to present the design rules in full, rather than to present only the differences between ICL's rules [1] and VTI's rules [6].  We have also decided to use more or less the same section numbering as VTI's design rule document [6], to facilitate cross reference.
1.5.  Issues
1.5.1.  Scaling
Both ICL's design rules [1] and VTI's old design rules [2] are nominally "lambda" design rules, implying that they can be scaled.  As it turns out, both are at the lower limit of their scalable ranges, with lambda equal to one micron.  In both cases, drawn gate lengths are two lambda (minimum), i.e., two microns.
VTI's new design rules [6] are designed to permit scaling to 1.6-micron gate lengths (lambda = 0.8 microns) eventually.  As of Rev *B, they are applicable to 2.0-micron gate lengths.  Now that the new rules exist, VTI would prefer we follow the new rules rather than the old rules, not only to permit scaling in the future but to improve yield at 2.0-micron gate lengths.  So that's what we're doing.
The main objective of this document is to make sure that multiple sourcing works for two-micron designs.  We have chosen not to guess what the lambda design rules might turn out to be, say, for 1.2-micron gate lengths and impose them on the current two-micron designs.
1.5.2.  Epi
Currently, ICL prefers to use epi wafers, while VTI uses non-epi wafers.  Thus, the VTI design rules require the designer to avoid the potential for latch-up by being very careful with layout, especially around pads and the periphery of the chip.
VTI may well switch to epi wafers at some time in the future.
1.5.3.  Acceptance Criteria
VTI will cheerfully fabricate wafers which are called acceptable if their process control monitor (PCM) chips work.
Alternatively, VTI would prefer to fabricate wafers, test the dice thereon with known-good test vectors supplied by us, and ship us dice that work, at an agreed-upon price per chip.  There are several problems with this approach, however.  We don't currently have a good way of generating known-good test vectors, and VTI is not staffed to provide a lot of tender loving care.  We don't know if our designs are good, i.e., capable of passing a test vector sequence.  At present, most of our designs have more pins than do VTI's testers, although there are workarounds, and VTI will be getting testers with more pins.
In any case, for the short term, we're probably stuck with having to accept wafers if the PCMs work.  Given that, it may be prudent to follow the VTI design rules as written.  The VTI guarantee is that if we follow the design rules and the PCMs work and our chips are logically correct, then our chips should work---and if they don't work then we have a valid complaint.  On the other hand, if we deviate from the design rules, even with VTI's knowledge and approval, the guarantee is less clear.
1.5.4.  Spinifex
In principle, it would probably be a good idea to change Spinifex to report VTI design rule violations as well as ICL design rule violations.  In practice, designers should be prepared to observe the VTI design rules without assistance from Spinifex, at least for the short term.
1.5.5.  Multi Project Wafers
The Dragon project needs to produce several chip designs, none in huge quantities.  For reasons of economy, it is desirable that several different designs be fabricated on each wafer. 
The use of 1X full-wafer masks and projection alignment lithography equipment is viewed as essential to producing many different chip designs per wafer economically.  Several different chip designs can be put on the same full-wafer mask, as Xerox PARC has been doing for some time, using the MPC or equivalent software.
Wafer stepper lithography equipment, which uses 5X reticles rather than 1X full-wafer masks,  is capable of higher resolution and more accurate overlaying than projection aligners.  However, a reticle exposes an area much smaller than the entire wafer.  (The stepper then steps the reticle image from site to site on the wafer, doing a separate alignment at each site.)  For example, ICL's stepper can expose a circular area 2.0 cm in diameter, and MEC's stepper can expose a circular area 2.9 cm in diameter.  The number of different designs which could be put on the same reticle is thus extremely limited.  For example, only one 11-mm square die would fit.  (That's the size Bill Gunning has been talking about for chips which use the custom PGA package he designed.)
Because reticles have to be entirely defect-free, they are more expensive than masks.  Wafer steppers could in theory use multiple reticle sets to expose multiple designs per wafer, but at ICL this would be awkward, because their stepper does not have an automatic mechanism for changing from one reticle to another.  Thus a separate wafer run might be required for each design.
Wafer steppers may be required for fabricating sub-two-micron circuits, although VTI has suggested that it has some (undisclosed) plans for fabricating some sub-two-micron circuits using their Perkin Elmer 500 projection aligners.  (It is also possible to contemplate using steppers for critical layers and projection aligners for non-critical layers.)
What all this means to the designer is that designs will be prototyped and debugged using projection aligners.  So those designs should use design rules appropriate for that lithography equipment.  That probably means the two-micron design rules should be used [1], [6].  But stay tuned for further developments.  Once a design is proven, conceivably the expense of fabricating it with steppers could be justified, and more aggressive design rules could be used.
Possible further developments:
o  ICL might get a stepper with a glass changer.
o  The cost of reticles may plummet.  Ateq, a start-up company, has introduced a laser-based reticle generator which is capable of higher throughput that E-beam pattern generators and costs less.  Moreover, because it uses optical photoresist rather than E-beam resist, the defect density ought to be much lower, reducing the cost of rework.  But it remains to be seen whether this potential will be realized in the form of lower prices from mask houses.
1.5.6.  Shared Masks
It is economically desirable to make a mask set that can be used by both ICL and VTI to fabricate chips.  This entails putting in separate alignment targets for ICL's P&E 341 and VTI's P&E 500 projection aligners, putting in separate process control monitor (PCM) chips, etc.  This should all be transparent to the designer.  Knock wood.  (Actually, as things stand, ICL and VTI require different masks for NWL and PWL, and perhaps DIF, but we think they can share everything else.)
1.5.7.  Players
In principle, we wouldn't mind having the capability of fabricating Dragon chips at more than two facilities.  Sharing masks more than two ways could prove interesting.  We haven't thought about it much.
2.  Scope
This section is more or less quoted from VTI's design rule document [6].
2.1.  Lambda
The layout rules defined here are adimensional and process independent.  They are adimensional because they are expressed in units of lambda, where one lambda is equal to one half the minimum feature size (usually the gate length dimension), and process independent because the same layout can be used to generate the set of masks required for the various processes listed in Section 3, providing that the layout contains the drawings of the P and N wells.
2.2.  Other Documents
This document refers to, but doesn't contain, information about the processes, the electrical characteristics of the devices and their models, and mask requirements.  The list of reference documents is given in the next section.
2.3.  Warning
Deviations from these rules require approval from the [VTI] Design Technology, Process, Development, Manufacturing, QA, and Reliability Departments [and also ICL's equivalent groups].
[The following subsections list the deviations we're planning to adopt.  We list only the areas in which we plan to be more aggressive than the rules allow, not where we plan to be more conservative.]
2.3.1.  Deviations From VTI Design Rules
o  The P+ to N+ minimum spacing across a well boundary is reduced from 12 lambda to 10 lambda.  See Sections 6.3.7. and  6.3.12.
o  The minimum transistor width of weak transistors is reduced from 3 lambda to 2 lambda.  See Section 6.3.2.
o  Vias are permitted to be partly on diffusion and partly on field oxide, but only when it's really necessary.  We understand that this is actually the intent of VTI's rule.  See Sections 6.7.1, 6.7.11., and 6.7.12.
2.3.2.  Differences In Appearance From VTI Design Rules
o  VTI and ICL would like to put the N-well electrical boundary in different places.  VTI would like it 2 lambda oversized from drawn, and ICL would like it 1 lambda undersized from drawn.  We deal with this difference by writing the design rules conservatively enough to cover both cases.  This affects N-well minimum width and spacing, rules for contacting the N-well and substrate, guard rings, dummy collectors, etc.  See Sections 6.1.1., 6.1.2., 6.1.3., 6.1.4., 6.2.2., 6.3.6, 6.3.9., 6.3.19., 7.5.2.2., 7.5.2.12., and 7.5.2.13.
2.3.3.  Deviations From ICL Design Rules
o  The minimum via size is reduced from 3 x 3 lambda to 2 x 2 lambda.  See Section 6.7.2.
o  The maximum via size is increased from 3 x 3 lambda to 5 x 5 lambda, but a 2-lambda metal surround is now required for vias larger than minimum size.  See Sections 6.7.3. and 6.7.5.
o  The maximum contact size is changed from 2 x N to 5 x 5, but a 2-lambda surround (of diffusion, poly, and/or metal) is now required for contacts larger than minimum size.  Also, a non-minimum size diffusion contact must now be 3 lambda from a gate.  See Sections 6.5.1.2., 6.5.1.4., 6.5.1.5., 6.5.1.6 and 6.5.1.8.
3.  Reference Documents
This section is more or less quoted from VTI's design rule document [6].  See also Section 1.3.
3.1.  Process Descriptions
3.1.1.  Two-Micron
o  "2.0-Micron N-Tub CMOS Process Description," Document Number 02-ECA20-4.
This is a single poly process with implanted N-Tub on P-Type substrate.  The P+ and N+ source/drain diffusions are very shallow because of the low temperature process used after their formation.  Minimum nominal gate length is 2.0 microns for both P and N channel devices.  Two types of complementary enhancement transistors are available and their thresholds are controlled by a single, non selective channel implant.  Gate oxide thickness is 400 Angstoms.
Process parameters and device electrical characteristics and models are described in the document entitled "Spice Models For the 2.0-Micron N-Tub Process," Document Number 16-00503.
3.2.  Tooling Specification
To be released.  [This probably refers to "Tooling Specification for 2.0 Micron N-Well CMOS Double Metal Advanced Lithography Design Rules," Document Number 02-10001, Rev **, June 7, 1985.  We have a copy, marked "Uncontrolled; No Automatic Distribution of Upgraded Revisions."  We are trying to get a more recent revision, which is known to exist.]
3.3.  Assembly Build
o  "Assembly Build Specification Preparation," Document Number 10-10007.
4.  Layout Information
We more or less quote from VTI's design rule document.
4.1.  All drawn dimensions are assumed to be equal to the final dimensions on the wafer.  [As an exception, N-well is drawn according to the ChipNDale convention, which does not correspond to a physical thing on the wafer.  See Section 11.3.]
4.2.  The layout rules given here are expressed in units of lambda and the minimum feature size is equal to two lambda units.
4.3.  All the drawings are done with all edge boundaries snapped to a grid, with a unit of the grid equal to 1/4 the minimum feature size allowed by the process chosen for the manufacturing of the circuit.
4.4.  The value of lambda in microns can take only discrete values which are dictated by the limitations imposed by the process and/or the lighographic equipment used, as specified in Section 4.8.
4.5.  A layout done according to these rules can be shrunk from a lambda = 1.0 microns to a lambda = 0.8 microns [at VTI, but not at ICL].  Since the process which allows the use of a lambda = 0.8 microns is still under development, no reference to it is made here.
4.6.  Bonding pad, scribe line and some of the layout rules for the layout of CMOS I/O are not shrinkable and are given in microns.
4.7.  Use of units of a snap grid size in a layout different from the ones listed in Section 4.8. is not allowed.
4.8.  Specification for Layout:
4.8.1.  Process:  2.0-micron N-well; minimum drawn gate:  2.0 microns; technology file:  CMN20A; lambda:  1.0 microns; layout snap grid size:  0.5 lambda.
5.  Drawn Layers
We more or less quote from VTI's document.  [Illustrations omitted.  We'll be using ChipNDale layers and objects instead.  So this section may not be of much interest.]
For a non-committed design (i.e., manufacturable using a P-well or N-well or twin-well process) the layers to be drawn are:
CNW	N-well       	Defines substrate of P-channel devices.
CPW	P-well       	Defines substrate of N-channel devices.
CR   	well resistor	[We won't have any of these.]
CPD	P+ diffusion	Defines P+ diffused and P-channel gate areas.
CND	N+ diffusion	Defines N+ diffused and N-channel gate areas.
CP   	Polysilicon	Defines poly gates and interconnect.
CC   	Contact      	Defines contact openings to diffusion and poly.
CM  	Metal1      	Defines first metal interconnects.
CC2 	Via           	Defines openings in the insulator between first and second metal.
CM2 	Metal2      	Defines second metal interconnects.
CG  	Pad window	Defines openings on the passivation layer for probing and bonding.
CB   	Butting      	[Artifical layer for flagging split contacts.  We won't do this.]
[VTI's document also lists layers EXCL, TEXT, and DCTY, without explanation.]
6.  Generalized Layout Rules
6.0.  General Rules
[Please excuse the strange section numbering; I wanted to put this section before the others, and also to retain the VTI section numbers.]
6.0.1.  Grid
All features must be drawn on a 0.5-lambda grid.
6.0.2.  Equipotential Shapes
In general, we adopt the policy that two shapes at the same electrical potential must obey the same design rules as they would have to obey if they were not at the same potential.
6.0.3.  Distance Metric
In general, the distances specified by the design rules are on-axis distances.  For example, the design rule for metal2 spacing is 4 lambda, meaning that one metal2 feature must be at least 4 lambda from another metal2 feature in either the x direction or the y direction.  In particular, if two metal2 shapes are separated by 3 lambda in the x direction and 3 lambda in the y direction, that's a design rule violation, even though the Euclidian distance between them is 4.242 lambda.
6.1.  Well Rules
6.1.1.  Minimum Width
  o  Well minimum width:  12 lambda.
ICL's rule is that the the minimum width of the electrical boundary is 8 lambda.  This corresponds to a drawn N-well minimum width of 10 lambda and a mask minimum width of 2 lambda, since the boundary outdiffuses 3 lambda per side.  However, ICL is a little nervous about this.  The N-well mask normally is not inspected closely to make sure minimum feature critical dimensions are correct.  Also, since the area into which the N-well dopant is implanted is small compared to the area inside the final electrical boundary, there is some concern that the final dopant concentration might be lower than it is for larger N-wells.  We therefore choose 12 lambda as the drawn minimum width.  This corresponds to a mask minimum width of 4 lambda.
Most of the N-wells used by the Dragon project will contain transistors, which will force the N-wells to be larger than minimum width anyway.  So we're not too concerned about the area penalty for using the more conservative rule.  N+ dummy collectors will get larger however.  We don't presently seem to be using N-well resistors.
By the way, VTI's rule is that the width of the area into which the N-well dopant is introduced is at least 4 lambda.  (Following this rule, VTI would draw minimum width N-well at 4 lambda, but we would draw it at 12 lambda.)
Because ICL requires that the N-well electrical boundary be 1 lambda undersized from drawn and VTI requires that it be 2 lambda oversized from drawn, ICL's minimum width rule is the applicable rule. 
6.1.2.  Minimum Spacing
o  Well minimum space:  10 lambda.
ICL's rule is that the minimum spacing between electrical boundaries is 10 lambda.  This corresponds to a drawn N-well minimum spacing of 8 lambda.
VTI's rule is that the minimum spacing between areas into which N-well dopant is implanted is 12 lambda.  The corresponding minimum spacing between electrical boundaries is 6 lambda.  To meet VTI's requirement that their electrical boundary be 2 lambda oversized from drawn, we have to draw it at 10 lambda.
(VTI actually has different rules for N-well spacing, depending upon whether the N-wells are at the same potential or not.  We simply adopt the more conservative rule universally.)
6.1.3.  Under Bonding Pads
o  Well surrounds metal1 of bonding pad:  0 lambda.
VTI requires that wells be placed under most bonding pads.  For an N-well process, put an N-well under all pads except for VSS pads.  For P-well and twin-well processes, put a P-well under all pads except for VDD pads.
VTI's version of this rule says 0 lambda.  ICL has no such rule, so we're not trying to follow the rule for ICL's version of N-well electrical boundary placement.  Privately, VTI confesses there is probably no good reason for this rule.  It may have originated because it was felt that the well would provide isolation of metal from substrate if the chip were cracked during bonding.  But VTI says it does not crack chips during bonding anyway, and that if it did, this measure would be insufficient.  However, the rule seems to stay on the books because it doesn't cost anything.
6.1.4.  Minimum Spacing of P-Well from N-well
o  P-well avoids N-well:  ? lambda.
VTI's rule is that the spacing between the areas into which the P and N dopants, respectively, are implanted is 3 lambda.  We postpone further discussion, since we are primarily interested in N-well technology, and we don't yet draw P-well.
6.2.  Well Resistor Rules
The Dragon project is not using well resistors at the moment.  Given that we want to fabricate chips at both ICL and VTI, and that they would like the electrical boundary of N-well in different places, so there would be considerable variation in resistance between resistors fabricated at the two facilities, it's probably just as well that we don't use well resistors.  We include this section because VTI has such a section in their design rules.  Actually, all these rules are redundant, in that there is an equivalent rule in Section 6.1.
6.2.2.  Minimum Width
o  Resistor Minimum Width:  12 lambda.
6.2.3.  Minimum Spacing
o  P-Well Resistor Avoids P-Well:  10 lambda.
6.2.4.  Minimum Spacing
o  N-Well Resistor Avoids N-Well:  10 lambda.
6.2.5.  Minimum Spacing
o  Resistor Minimum Spacing:  10 lambda.
6.3.  Diffusion Rules
6.3.1.  Minimum Width
o  Diffusion Minimum Width:  2 lambda.
This rule applies to diffusion bounded on both sides by field oxide.  Actually, diffusion might also be bounded by poly or diffusion of the opposite type.  So there are six combinations of field oxide, poly, and diffusion of the opposite type that could determine the width of a diffusion; and thus there are six design rules.  (Some of these rules are not VTI design rules, so we adopt something reasonable.)
o  Diffusion Minimum Width (Field Oxide and Poly):  3 lambda.  See Section 6.3.18.
o  Diffusion Minimum Width (Poly and Poly):  2.5 lambda.  See Sections 6.4.3. and 6.3.18.
o  Diffusion Minimum Width (Field Oxide and Opposite Diffusion):  3 lambda.
o  Diffusion Minimum Width (Poly & Opposite Diffusion):  3 lambda.  See Section 6.5.2.3.
o  Diffusion Minimum Width (Both Sides Opposite Diffusion):  3 lambda.
6.3.2.  Transistor Minimum Width
o  Transistor Minimum Width:  3 lambda.
o  Weak Transistor Minimum Width:  2 lambda.
The VTI rules do not explicitly permit weak transistors to have a minimum width of 2 lambda, but they have fabricated both P-channel and N-channel test transistors that work.  The main reason weak transistors were not permitted by the rules is that they haven't been accurately modelled and because there can be a large variation in electrical parameters.  In applications such as weak pull-ups, where electrical performance is not critical, we have decided to permit such transistors.  ICL rules permit weak transistors explicitly.
6.3.3.  Diffusion Minumum Spacing
o  Diffusion Minimum Spacing:  3.5 lambda.
This VTI rule applies to P+ to P+, N+ to N+, and P+ to N+ spacing, whenever the two adjacent diffusions are located on the same substrate (or well) and one or both are intended to be isolated from the substrate (or well).
ICL's rule is 3 lambda, but we adopt VTI's more conservative rule of 3.5 lambda.
6.3.4.  Diffusion Minimum Spacing
o  Diffusion Minimum Spacing, Special Case:  0 or 3.5 lambda.
This VTI rule applies to P+ to N+ spacing, whenever the two adjacent diffusions are located on the same substrate and the diffusion of the opposite type of the substrate (or well) is at the same potential as the substrate (or well).
6.3.5.  N-Well Surrounds P+
o  N-Well Surrounds P+ Diffusion:  5 lambda.
See Section 6.3.12.
6.3.6.  N-Well Surrounds N+ Contact
o  N-Well Surrounds N+ Contact:  4 lambda.
VTI's rule is that N+ contact should "overlap" the area into which N-well dopant is implanted by 3 lambda.  But from the accompanying diagram, it would appear that VTI wants the implanted area to "surround" N+ contact by 3 lambda, not just "overlap."  (See Section 11.2 for our definitions of "surround" and "overlap.")  Because VTI's area into which N-well dopant is implanted is 1 lambda undersized from drawn, VTI's rule is that, as drawn, N-well must surround N+ by 4 lambda.
VTI's reason for wanting N-well to surround N+, rather than just overlapping it, is that in addition to assuring that the N+ makes an electrical connection to the N-well, the rule assures that the N+ will not form, with the P- substrate, a reverse biased diode between VDD and ground.  Such a diode, if made on the site of a defect in the silicon, could exhibit excessive leakage.  This kind of failure might show up right away, adversely affecting yield, or later on, adversely affecting long-term reliability.  Of course, N-channel transistors in the substrate form exactly this kind of diode, and are sometimes biased between VDD and ground.  But in that case, the risk is unavoidable.
For this reason, VTI does not use guard rings for internal circuitry in its own designs, although it provides design rules for them that are less stringent than the rule for for N-well contacts.
ICL has no explicit rule.  Since ICL's N-well electrical boundary is 3 lambda undersized from VTI's N-well electrical boundary,  our version of VTI's rule would be that N-well should surround N+ contact by 7 lambda.  But ICL feels that this is overly conservative and is willing to go along with the 4 lambda rule.
6.3.7.  N-Well Avoids N+
o  N-Well Avoids N+ Diffusion:  5 lambda.
VTI's rule here is 7 lambda.  We have decided to adopt ICL's more agressive rule, because we think we could use the space, and because we think there is no technological reason not to do so.  See Section 6.3.12.
6.3.8.  N-Well Overlaps N+ Guard Ring
o  N-Well Overlaps N+ Guard Ring:  5 lambda.
VTI's rule is that N+ guard ring should overlap the area into which N-well dopant is implanted by 1 lambda.  So it must overlap drawn N-well by 2 lambda.
ICL doesn't have an explicit rule.  Since ICL's N-well electrical boundary is 3 lambda undersized from VTI's N-well electrical boundary, the analagous rule would be 5 lambda.
Note that in this context, the term "overlap" is used in an unusual way, which is discussed further in Section 11.2.
Warning:  VTI doesn't use guard rings for internal circuitry in its own designs, because they think yield and long-term reliability are adversely affected.  See Section 6.3.6.
6.3.9.  N-Well Avoids P+ Contact
o  N-Well Avoids P+ Contact:  4 lambda
VTI's rule is that P+ contact avoids the area into which N-well dopant is implanted by 5 lambda.  Since VTI's implanted area is undersized from drawn N-well by 1 lambda, our version of the rule would be that P+ contact avoids N-well by 4 lambda.
VTI's reason for wanting substrate (absence of N-well) to surround P+, rather than just  overlapping it, is analogous to their reason for wanting N-well to surround N+.  It enhances yield and long-term reliability.  See Section 6.3.6.
ICL has no explicit rule.  Since ICL's N-well electrical boundary is 3 lambda undersized from VTI's N-well electrical boundary, the analagous rule would be 1 lambda.
6.3.10.  N+ Guard Ring Avoids P+ Contact
o  N+ Guard Ring Avoids P+ Contact:  4 lambda.
This is VTI's rule.  We're not sure why it is required.  (If this rule did not exist, rule 6.3.3. would require the separation to be at least 3.5 lambda.)  But we're not going to argue.
6.3.11.  P-Well Surrounds N+
Discussion is deferred for now, since we don't draw P-well yet.
6.3.12.  P+ to N+ Minimum Spacing
o  P+ to N+ Minimum Spacing Across Well Boundary:  10 lambda.
This spacing is the sum of the spacings specified by rules 6.3.5. and 6.3.7., and also the sum of the spacings specified by rules 6.3.11. and 6.3.14.
VTI's rule here is 12 lambda.  We have decided to adopt ICL's more aggressive rule, because we think we could use the space, and because we think there is no technological reason not to do so.  VTI has said there's probably no problem with the 10 lambda spacing, although they won't change their rules officially.
The purpose of the rule is apparently to protect against latch-up.  Tests on test structures, done independently by VTI and ICL, indicate that for bulk silicon, such as VTI uses, the difference between a 10-lambda space and a 12-lambda space, in terms of latch-up susceptiblity, is negligible.  In either case, latch-up will be sustained once it is triggered, so it is essential not to trigger latch-up in the first place.  For epitaxial silicon, such as ICL uses, latch-up susceptibility is an order of magnitude less than it is for bulk silicon, so ICL's 10-lambda spacing should be sufficient.
6.3.13.  P-Well Overlaps P+ Contact
Discussion is deferred for now, since we don't draw P-well yet.
6.3.14.  P-Well Avoids P+
Discussion is deferred for now, since we don't draw P-well yet.
6.3.15.  P-Well Overlaps P+ Guard Ring
Discussion is deferred for now, since we don't draw P-well yet.
6.3.16.  P+ Guard Ring Avoids N+ Contact
o  P+ Guard Ring Avoids N+ Contact:  4 lambda.
This is VTI's rule.  We're not sure why it is required.  (If this rule did not exist, rule 6.3.3. would require the separation to be at least 3.5 lambda.)  But we're not going to argue.
6.3.17.  N- Substrate Overlaps N+ Contact
Discussion is deferred for now, since the rule applies only to P-well technology, and we don't yet draw P-well.
6.3.18.  Source/Drain Extension
o  Source/Drain Diffusion Extends Beyond Gate:  3 lambda.
VTI's rule says that the minimum overlap of a P+ or N+ source/drain diffusion across a gate (in the direction of current flow) is 3 lambda.  The idea is that if the source or drain area is bounded on one side by poly and on the other side by field oxide, and if it is required to carry current parallel to the gate, then its minimum drawn width must be 3 lambda.  This takes into account that due to misalignment the actual width of this source or drain diffusion may be less.  If this diffusion is required to carry substantial current parallel to the gate, then 3 lambda may not be wide enough, but this is left to the designer's judgment.
ICL's rule is that source/drain diffusion extends beyond gate by at least 2 lambda.  The direction of current flow is not considered.  For simplicity, we adopt VTI's distance of 3 lambda and ICL's idea of not considering the direction of current flow.
Note that if the source/drain diffusion is bounded by poly on both sides, its width cannot be reduced due to misalignment, so the 2.5-lambda minimum poly spacing is sufficient for design rule purposes.  Again, if this diffusion is required to carry substantial current parallel to the gate, then 2.5 lambda may not be wide enough, but this is left to the designer's judgment.
If the source/drain diffusion is bounded on one side by poly and on the other side by diffusion of the opposite type, then the applicable design rule is 3 lambda.  See Section 6.5.2.3.
6.3.19.  Substrate Overlaps P+ Guard Ring
o  Substrate Overlaps P+ Guard Ring:  2 lambda??
VTI doesn't have an explicit rule.  (Rule 6.3.15. is similar, but refers to P-well.)
ICL doesn't have an explicit rule either.
Warning:  VTI doesn't use guard rings for internal circuitry in its own designs, because they think yield and long-term reliability are adversely affected.  See Section 6.3.6.
6.3.20.  Angle Transistors
VTI doesn't have an explicit rule, but we explicitly permit the gate of a transistor to have (zero or more) 90-degree bends.  VTI has indicated that this is OK.  In principle, one might worry that the higher electric fields at the corners might cause problems with hot electrons or punchthrough.  But ICL tests indicate that it is not a problem in practice.
The effective width of an angle transistor is difficult to estimate accurately, but it is at least as wide as the length of the interior edge of the poly over diffusion.  Perhaps the length of the centerline of the poly is a better estimate of the transistor's width.
6.4.  Polysilicon Rules
6.4.1.  Poly Minimum Width
o  Poly Minimum Width:  2 lambda.
6.4.2.  Minimum Transistor Length
o  Poly Minimum Transistor Length:  2 lamabda.
6.4.3.  Minimum Spacing
o  Poly Minimum Spacing:  2.5 lambda.
ICL's rule is 2.0 lambda, but we adopt VTI's more conservative rule of 2.5 lambda.
6.4.4.  Minimum Gate Extension
o  Poly Gate Extends Beyond Diffusion:  2 lambda.
6.4.5.  Minimum Spacing to Unrelated Diffusion
o  Poly Avoids Unrelated Diffusion:  1 lambda.
For the purposes of these rules, poly can be "related" to diffusion only by forming a transistor, not by being at the same electrical potential.  In particular, buried contacts are illegal.  And butting contacts are also illegal.  (A "butting" contact is a contact that connects poly and diffusion, formed by overlapping poly and diffusion, and putting a contact cut over both the poly and the diffusion.  Such contacts represent a long-term reliability problem [9, p 191].)  (VTI calls split contacts "butting contacts." Split contacts are legal.  See Section 6.5.2.)
6.5.  Contact Rules
6.5.1.  Contact To P+ And N+ Diffusion And Poly
6.5.1.1.  Minimum Contact Size
o  Minimum Contact Size:  2 x 2 lambda.
6.5.1.2.  Maximum Contact Size
o  Maximum Contact Size:  5 x 5 lambda.
VTI's rule is 5 x 5 lambda.  ICL's rule is that the width must be 2 lambda, but the length is unrestricted.  The motivation behind these rules is as follows.  In order to expose 2 x 2 lambda contacts correctly, the level of illumination must be such that larger contacts will be overexposed and will hence will be produced larger than drawn.  This would normally subtract from the tolerance of the overlap (surround) rules 6.5.1.4. and 6.5.1.5.  But we have decided to make the overlap rules more complicated, so that minimum size contacts can have aggressive surrounds and non-minimum size contacts can still be used, although with more conservative surrounds.
6.5.1.3.  Minimum Contact Spacing
o  Minimum Contact Spacing:  3 lambda.
ICL's rule is 2 lambda, but we adopt VTI's more conservative rule of 3 lambda.
6.5.1.4.  Minimum Poly Surround of Contact
o  Poly Surrounds Contact:  1 lambda, if contact is minimum size; 2 lambda otherwise.
VTI's rule is that 1-lambda surround is sufficient for all permitted contact sizes.  ICL's rule is that 1-lambda surround is sufficient for contacts up to 2 x N lambda, but they have expressed some concern about holding surround tolerances for, say, 2 x 5-lambda contacts, and believe that a 1-lambda poly surround of, say, a 5 x 5-lambda contact may well not be adequate.
We adopt the rule stated here because we think it addresses ICL's concern about producing contacts larger than minimum size.  We think that when contacts larger than minimum size are required, the larger surround will not be a major drawback.
We note that VTI and ICL rules are quite aggressive compared to the rest of the industry.
During circuit fabrication, if poly fails to surround contact, the etchant used to make the contact cut, which normally stops on poly, can etch into the adjacent field oxide, creating a "garbage pit," which can lead to metal1 step coverage problems later on.
6.5.1.5.  Minimum Diffusion Surround of Contact
o  Diffusion Surrounds Contact:  1 lambda, if contact is minimum size; 2 lambda otherwise.
The discussion in Section 6.5.1.4. also applies here.  VTI and ICL rules are quite aggressive compared to the rest of the industry.
During circuit fabrication, if diffusion fails to surround contact, the etchant used to make the contact cut, which normally stops on diffusion, can etch into the adjacent field oxide.  If the etchant etches completely through the field oxide to the substrate (well), the resulting contact cut will allow metal1 to short to the substrate.  In fact, even if the diffusion does surround contact, but by an inadequate amount, a short to the substrate may still occur, due to electromigration, after the device has been tested good and installed in a system.
6.5.1.6.  Minimum Diffusion Contact to Gate Spacing
o  Cut (Contact to Diffusion) Avoids Poly Gate:  2 lambda if contact is minimum size; 3 lambda otherwise.
VTI's rule is 1.5 lambda.  We adopt the more conservative rule stated.
6.5.1.7.  Minimum Poly Contact to Diffusion Spacing
o  Cut (Contact to Poly) Avoids Diffusion:  2 lambda.
6.5.1.8.  Minimum Metal1 Surround of Contact
o  Metal1 Surrounds Contact:  1 lambda if cut is minimum size; 2 lambda otherwise.
Again, the discussion in Section 6.5.1.4. applies.
6.5.2.  Split Contact
6.5.2.1.  Definition
A split contact is a single contact which extends over both a transistor source diffusion and a diffusion of the opposite type, used for contacting the substrate (or well), which are butted together.  VTI calls this a "butting contact," but this term should probably be avoided, because that is the term ICL uses for contacts which overlap both diffusion and poly.  Incidently, the latter kind of butting contact is not permitted.
6.5.2.2.  VTI Drawing Conventions
VTI has some conventions for drawing split contacts, using a separate "butting" layer, but this is not of interest to use Chipndale for layout. 
6.5.2.3.  Gate to Opposite Diffusion Spacing
o  Gate Avoids Substrate (or Well) Contact Diffusion:  3 lambda.
The intent of this rule is to assure that the transistor source diffusion between the gate and the substrate (or well) is wide enough to carry current.
6.5.2.4.  Minimum Split Contact Width
o  Minimum Split Contact Width:  2 lambda.
6.5.2.5.  Minimum Split Contact Size
o  Minimum Split Contact Size:  2 x 6 lambda.
Rule 6.5.1.5. also applies to the diffusion surround for split contacts, in the following way:  since a 2 x 6-lambda split contact is minimum size for split contacts, a 1-lambda diffusion surround is permitted.  Part of the reason we can do this is that for normal contacts the surround rule is designed to ensure that the contact is not shorted to the substrate (or well), but for split contacts, the intent is to short to the substrate (or well).
6.5.2.6.  Maximum Split Contact Size
o  Maximum Split Contact Size:  2 x 6 lambda.
VTI's rule is that the maximum size can be 5 x 10 lambda.  ICL's rule is that the maximum contact width is 2 lamabda, but that the length is unrestricted.  However, ICL is a little nervous about their rule, so we've agreed to adopt 2 x 6 lambda as the maximum size.
6.5.2.7.  Minimum Overlap of Split Contact and Diffusion
o  Minimum Overlap of Split Contact and Diffusion:  3 lambda.
6.5.2.8.  Minimum Metal1 Surround of Contact
o  Minimum Metal1 Surround of Contact:  1 lambda.
6.6.  Metal1 Rules
6.6.1.  Metal1 Minimum Width
o  Metal1 Minimum Width:  3 lambda.
VTI's rule is 2 lambda, but we adopt ICL's more conservative of 3 lambda.
6.6.2.  Metal1 Minimum Spacing
o  Metal1 Minimum Spacing:  3 lambda.
6.6.3.  Metal1 Maximum Current Limit
o  Metal1 Maximum Current Limit:  0.5 mA/micron of width.
ICL's rule is 1.0 mA/micron of width, but we adopt VTI's more conservative rule.
6.7.  Via Rules
6.7.1.  Via Permitted Sites
Vias are usually permitted only on flat topology.  The following flat topologies are acceptable:  diffusion, poly, and field oxide.  When it is really necessary, a via is also allowed to be partly on diffusion and partly on field oxide.  A via is not permitted over a gate.  
This restriction is a VTI rule.  ICL had no such restriction.
6.7.2.  Via Minimum Size
o  Via Minimum Size:  2 x 2 lambda.
VTI's rule is 2 x 2 lambda.  ICL's rule is 3 x 3 lambda, but ICL has agreed to accept the smaller 2 x 2 lambda rule, provided we put vias only on flat topology.
6.7.3.  Via Maximum Size
Via Maximum Size:  5 x 5 lambda.
VTI's rule is 5 x 5 lambda.  ICL's rule is 3 x 3 lambda, but ICL has agreed to accept the larger via sizes, provided the metal surrounds are increased to 2 lambda for vias of non-minimum size.
6.7.4.  Via Minimum Spacing
o  Via Minimum Spacing:  4 lambda.
ICL's rule is 2 lambda, but we adopt VTI's more conservative rule of 4 lambda.
6.7.5.  Via Minimum Metal Surround
o  Metal1 Surrounds Via:  1 lambda if via is minimum size; 2 lambda otherwise.
o  Metal2 Surrounds Via:  1 lambda if via is minimum size; 2 lambda otherwise.
VTI's rule is 1 lambda for all cases.  ICL's official rule is 1 lambda, but only for the minimum-size via, which is 3 x 3-lambda.  We adopt the stated rules because we think that it provides sufficient margin for ICL to make both minimum-sized (2 x 2-lambda) vias and larger vias.
6.7.6.  Minimum Spacing to Poly
o  Via on Field Oxide Avoids Poly:  2 lambda.
We adopt VTI's rule.
6.7.7.  Minimum Poly Surround
o  Poly Surrounds Via on Poly:  3 lambda.
We adopt VTI's rule.
6.7.8.  Minimum Spacing to Diffusion Contact
o  Via Avoids Contact to Diffusion:  2 lambda.
We adopt VTI's rule.
6.7.9.  Minimum Spacing to Poly Contact
o  Via Avoids Contact to Poly:  3 lambda.
6.7.10.  Maximum Current Limit
o  Via Maximum Current Limit:  0.07 mA/micron of perimeter.
We adopt VTI's rule; ICL didn't have a corresponding rule.
6.7.11.  Minimum Spacing to Diffusion
o  Via on Field Oxide Avoids Diffusion:  2 lambda (advisory).
This rule no longer appears explicitly in the VTI design rules [6].  VTI would like us to follow the rule whenever we can.  But when it's really necessary to do so, the rule can be violated.

6.7.12.  Minimum Diffusion Surround
o  Diffusion Surrounds Via on Diffusion:  2 lambda (advisory).
This rule no longer appears explicitly in the VTI design rules [6].  VTI would like us to follow the rule whenever we can.  But when it's really necessary to do so, the rule can be violated.

6.8.  Metal2 Rules
6.8.1.  Metal2 Minimum Width
o  Metal2 Minimum Width:  4 lambda.
VTI's rule is 3 lambda, but we adopt ICL's more conservative rule of 4 lambda.
Note:  an experiment is in progress, on run MPC5NA, to determine whether ICL can live with a 3 lambda minimum width for metal2.  A favorable outcome is expected.  Results are expected around February 1986.  Stay tuned.
6.8.2.  Metal2 Minimum Spacing
o  Metal2 Minimum Spacing:  4 lambda.
6.8.3.  Metal2 Maximum Current Limit
o  Metal2 Maximum Current Limit:  0.75 mA/micron of width.
VTI's rule is 1.0 mA/micron of width, but we adopt ICL's more conservative rule.
7.  Additional Layout Requirements
7.1.  Bonding Pads
7.1.1.  General Description
A bonding pad consists of a metal1 pad, a via opening, a metal2 pad, and openings into the passivation layers.
7.1.2.  Minimum Pad Dimensions
o  Minimum Pad Width for Metal:  127 microns.
VTI has this rule for plastic packages having 48 or fewer pins, as well as all non-plastic packages, and another rule, 157 lambda, for plastic packages having more than 48 pins.
7.1.3.  Minimum Metal Surround of Pad Via
o  Minimum Metal1 Surround of Pad Via:  3.5 microns.
o  Minimum Metal2 Surround of Pad Via:  3.5 microns.
7.1.4.  Minimum Metal2 Surround of Overglass Cut
o  Minimum Metal2 Surround of Overglass Cut:  5.0 microns.
7.1.5.  Minimum Pad Spacing
o  Minimum Pad Spacing:  72 microns.
7.1.6.  Minimum Overglass Cut Width
o  Minimum Overglass Cut Width:  117 microns.
VTI has this rule for plastic packages having 48 or fewer pins, as well as all non-plastic packages, and another rule, 147 lambda, for plastic packages having more than 48 pins.
7.1.7.  Minimum Nitride Passivation Cut Width
o  Minimum Nitride Passivation Cut Width:  107 microns.
VTI has this rule for plastic packages having 48 or fewer pins, as well as all non-plastic packages, and another rule, 137 lambda, for plastic packages having more than 48 pins.
7.1.8.  Minimum Spacing to Unrelated Metal
o  Minimum Spacing from Pad to Unrelated Metal:  30 microns.
As an exception to this rule, the metal1 and metal2 guard rings in the scribe line must be further away.  See Section 7.2.
7.1.9.  Minimum Spacing to Unrelated Features
o  Minimum Spacing from Pad to Unrelated Diffusion, N-well, Poly, Contact, or Via:  30 microns.
As an exception to this rule, the scribe line edge must be further away.  See Section 7.2.

7.1.10.  Bond Pad Fillet Options
7.1.10.1.  Options for Minimum Width of Wide Metal Entering Pad
o  Option A:  one metal trace:  51 microns.
o  Option B:  two metal traces:  25 microns each.
VTI offers an option C, but it involves a 45-degree angle, so we've left it out.
7.1.10.2.  Minimum Length of Wide Metal Entering Pad
o  Minimum Length of Wide Metal Entering Pad:  36 microns.
7.1.10.3.  Minimum Metal Width Leadaway After Wide Metal
o  Minimum Metal Width Leadaway After Wide Metal:  10 microns.
7.1.10.4.  Spacing from Passivation Cut to Edge of Wide Metal
o  Minimum Spacing of Passivation Cut to Edge of Wide Metal:  46 lambda.
7.1.10.5.  Minimum Opening in Pad Metal
Minimum Opening in Pad Metal:  12 microns.
7.2.  Scribe Line
We omit this section, since designers don't have to draw the scribe line.
7.3.  Bond Pad Placement
We omit this section, since it mostly talks about packages we don't intend to use for Dragon.
7.4.  Artifacts
We more or less quote from VTI's document.
7.4.1.  Purpose
These are general rules and information on the generation and placement of artifacts.  Artifacts are the structures that are placed on the chip for identification, copyright, and revision.  These structures should be generated using the CMOS cell compilers listed below, or equivalent layout drawn by hand.  See the HCMOS Cell Compiler Users' Manual for use of compilers.
7.4.2.  Generation From CMOS Cell Compilers (TM)
7.4.2.1.  CTEXT
Generates user-specified text strings.  The drawn layer of the text, and the size of the text geometries are cell parameters.  This cell can be used to imprint miscellaneous text on a drawn layer.
7.4.2.2.  CLOGO
Generates a "VTI" logo in the top layer metal.  Its size is parameterized for magnification factors 1 through 5.
7.4.2.3.  CFNLAY
Generates a revision letter of each mask layer within a particular chip design.  This cell is used to track the changes that affect different mask layers.
7.4.2.4.  CFNDEV
Generates text for the device numbers.  Allows 4 digit device number and 0-2 character revision or variant.
7.4.2.5.  CTMARK
Generates the trademark symbol and "VTI".  This must be used as is!  Copyright protected through VTI.  Do not edit.  [These instructions apply to VTI designers, not us.  It's interesting to note that they have thought this through.]
7.4.3.  General Rules For Use Of Artifacts
7.4.3.1.  Placement
Recommended area for placement is the lower left quadrant of the chip.  All chips should have at least a device number placed.  Since artifacts are drawn with exclude layers to avoid false errors, care must be taken in their placement, to insure that no design rules are violated.  A distance of at least 10 lambda is required between the artifacts and other non-related geometry.  Artifacts placed in pad areas must obey pad layout and bonding rules.  The placement of artifacts between pads is not recommended.
7.4.3.2.  Layers
All layers can be used except for CG, the pad window.  The foundry cell compilers control the use of layers.
7.4.3.3.  Revisions
Revision numbers should be placed only on layers that have been revised.  Revisions of derived layers are additionally tracked on the layers of origin.
NOTE:  Revision of certain layers may require retooling of derived layers.
7.5.  Layout Rules for CMOS
7.5.1.  Purpose
The purpose of Section 7.5. is to provide a set of rules which must be followed in the layout and placement of structures which are used as interfaces between the internal gates and the bonding pads.
7.5.2.  General I/O Pad Cell Layout Rules
The following rule apply to both the input protection pad cells as well as the output buffer pad cells.  The rules treat the input diodes and the diodes that result from an output buffer pad cell as being the same.  The term P+/N- well diode can be viewed as the P MOS output buffer device and the N+/P- substrate (or P-well) diode as the N MOS output buffer device.
The input protection device proposed is for both the N-well and P-well processes and is the double diode type.  It, or a version of it, will eventually be a cell in the [i.e., VTI's] CMOS cell library.
The terms "guard ring" and "dummy collector" are used in the following rules.  A guard ring is a diffusion ring (the same polarity diffusion as the well it rings) that surrounds and overlaps a well.  It is needed to reduce the well-to-power-supply resistance.  A dummy collector is coincident well and diffusion (again the same polarity diffusion as the well) that is used to reduce the beta product of the SCR structure.  Dummy collectors are usually placed between guard ringed wells that contain transistors.
7.5.2.1.  Separating N+ and P+
The bonding pad must be placed between the N+/P- diode (or N-channel output driver) and the P+/N- diode (or P-channel output driver).  This rule forces a separation of at least 187 microns, i.e.,the pad width plus twice the spacing from pad to unrelated features.
Over the phone VTI is not adamant about this rule, but suggests it as a guideline.
7.5.2.2.  Guard Rings
All wells in the pad areas must have strapped guard rings, where the guard ring diffusion must be surrounded by the well, as described in the following paragraphs.  All unused areas of a well must be filled with guard ring type diffusions.
In the N-well case, the VTI rule seems to be that the area into which N-well dopant is implanted must surround the N+ by 3 lambda.  In other words, it seems to be the same as the rule for N-well contacts.  No doubt this is done to enhance yield and long-term reliability, as explained in Section 6.3.6.  Because the area into which the N-well dopant is implanted is  1 lambda undersized from drawn, VTI's rule is that, as drawn, N-well must surround N+ by 4 lambda.
ICL has no explicit rule.  Since ICL's N-well electrical boundary is 3 lambda undersized from VTI's N-well electrical boundary, our version of VTI's rule would be that N-well should surround N+ contact by 7 lambda.  But ICL thinks that's too conservative and is willing to go along with VTI's 4 lambda.
In the substrate case, it might be reasonable to assume that the applicable rule was the same as the rule for substrate contacts.  See Section 6.3.9.  If so, then substrate must surround P+ by 4 lambda.
7.5.2.3.  Well Spacing
A P-well (or substrate) that contains N+ diffusions must be spaced 60 microns from the edge of the N-well that contains the P+/N- input protection diode structure.  Similarly, an N-well that contains P+ diffusions must be placed 60 microns from the edge of the P-well (or substrate) that contains the N+/P- input protection diode structure.
7.5.2.4.  Dummy Collectors
The P+/N- input protection diode must be completely surrounded by a P+/P- dummy collector hardwired to VSS.  Likewise, the N+/P- input protection diode must be completely surrounded by an N+/N- dummy collector hardwired to VDD.
7.5.2.5.  Separate Wells
The N-well of the P+/N- input protection diode cannot be merged with the N-well of any other device, and the edges of any other device's N-well which are within 60 microns must have a minimum width strapped P+/P- dummy collector hardwired to VSS between.  Likewise, the P-well of the N+/P- input protection diode cannot be merged with the P-well of any other device, and the edges of any other device's P-well which are within 60 microns must have a minimum width strapped N+/N- dummy collector hardwired to VDD between.  (For N-well CMOS technology, one cannot help but let the substrates "merge," but the dummy collector is required if the pseudo P-wells get too close.)
7.5.2.6.  More Isolation
The following must always be present between the N+ guard ring of the P+/N- input protection diode and any other N+ diffusion in a P-well (or substrate):
o  A P+/P- dummy collector hardwired to VSS.
o  An N+/N- dummy collector hardwired to VDD.
o  A P+ guard ring hardwired to VSS.
Likewise, the following must always be present between the P+ guard ring of the N+/P- input protection diode and any other P+ diffusion in an N-well:
o  An N+/N- dummy collector hardwired to VDD.
o  A P+/P- dummy collector hardwired to VSS.
o  An N+ guard ring hardwired to VDD.
It is recommended to adjust the widths and shapes of the dummy collectors in such a way that very little field oxide area is left between the guard rings of the input protection structure.
7.5.2.7.  Dummy Collectors for Pad Cells
A set of dummy collectors, each 15 microns wide, is required along the top of the pad cells, i.e., along the side closest to the edge of the chip.
Actually, we're not sure we'll follow this VTI rule exactly, since some of our chips use two rings of pads, but we include it here for advisory purposes.
7.5.2.8.  Dummy Collectors for Pad Cells, Continued
The pad cells should be designed such that all the dummy collectors abut and create a continuous ring around the chip.
7.5.2.9.  Still More Isolation
Guard rings and a set of minimum width dummy collectors are needed between a P-well (or substrate) and N-well if the midpoint between them is closer than 75 microns from the well edge of either type of input protection diode.
7.5.2.10.  More Guard Rings
The first well edge, parallel to the scribe line, encountered in going from a pad cell toward the center of the chip, regardless of its type or distance from a pad cell, must have a metal-strapped guard ring.
7.5.2.11.  More Pad Cells
If the pad cells are constructed so that its wells lie on the left and right sides of the bonding pad, instead of the top and bottom, then the pad cells must be alternately flipped so as to abut only to the same type wells and never to abut a P-well to an N-well.
7.5.2.12.  Minimum Spacing
The spacing between guard ring and/or dummy collector diffusions is 8 lambda.
The VTI rule is 6 lambda, but we should leave some extra room to accomodate both VTI's and ICL's placement of the N-well electrical boundary.
7.5.2.13.  Minimum Width Dummy Collector
A minimum width dummy collector is built from the following:
o  Diffusion:  4 lambda.
o  Metal1:  4 lambda.
o  Contacts:  2 x 2 lambda.
In addition, if it is a P+ dummy collector, for N-well and twin-well technologies, the dummy collector will have:
o  N-well:  12 lambda.
Likewise, if it is an N+ dummy collector, for P-well and twin-well technologies, the dummy collector will have:
o  P-well:  (not sure how wide; VTI says 4 lambda, but we may have a problem with its placement as well.)
7.5.2.14.  Sources and Contacts
Any source diffusion that is hardwired to a well (or substrate) power supply must be no further than 30 microns from the nearest well (or substrate) contact.  If is preferable that each such source be 0 microns from the nearest well contact, i.e., that a split contact be used.
7.5.2.15.  Wells Under Pads
Wells are placed under most pads.  See Section 6.1.3.  The well drawn below a bonding pad must be floating.  It cannot be connected to any signal or power supply line.  The  minimum spacing from active circuitry to the edge of the tub drawn below the pads is 30 microns.
7.5.2.16.  Down Bonds
VTI has a rule about down bonds, which doesn't seem to apply to the kinds of packages used on Dragon, so we omit it here.
7.5.2.17.  Warning
Large switching current spikes can cause voltage drops along the power bus lines that can forward bias a diffusion-to-well junction, which may cause a parasitic SCR to latch up.  The bus line widths should be designed with this in mind.
7.5.3.  Internal Logic Layout Rules
7.5.3.1.  Well and Substrate Contacts
All internal wells must have well contacts no further apart than 75 microns.  Moreover, the substrate must have substrate contacts no further apart than 75 microns, in those areas where the substrate contains transistors.
7.5.3.2.  Sources at Rails
Any transistor source diffusion which is wired to the well power supply must be no further than 30 microns from the nearest well contact.  It is preferable that each such source be 0 microns from the nearest well contact, i.e., that a split contact be used.
ICL has no corresponding design rule, but ICL's Richard Bruce says that this distance should be as short as possible.  ICL did some tests [10] in which latch-up was induced by driving an N+ souce higher than VDD, and the amount of current required to induce latch-up was measured as a function of the spacing between a nearby P+ source and its N-well contact.  It was found that, for a spacing of zero microns, the amount of current required to induce latch-up was four times that required for a spacing of 30 microns.  VTI simply requires that internal logic circuits be designed so that this sort of latch-up-inducing event does not occur.  (See Section 7.5.3.3.)  But it seems prudent to design in extra insurance where possible.
7.5.3.3.  Forward Bias Junctions
Any junction that has the possibility of becoming forward biased (diodes, PNP transistors, pull-down devices, etc.), and that is drawn in the internal logic area, must be drawn using the pad ring layout rules described above.  See Section 7.5.2.
7.5.3.4.  Power Distribution
Never tap power off the well or its guard rings for a logic node.
7.5.3.5.  Isolation from Periphery
The first well edge, parallel to the scribe line, encountered in going from a pad cell toward the center of the chip, regardless of its type or distance from a pad cell, must have a metal-strapped guard ring.
7.5.3.6.  Guard Rings
Guard rings and a set of minimum width dummy collectors are needed between an N-well and P-well (or substrate), if the midpoint between them is closer than 75 microns from the N-well or P-well (or substrate) of an input protection diode or output driver, 
7.5.3.7.  Dummy Collectors
If there is space available, place a set of dummy collectors between the pad ring area and the internal logic area.  The wider the collectors the better.
8.  Mask Definition Per Process and Relationship to the Drawn Layers
We omit this section, since designers don't really have to know.
9.  Critical Dimension Requirements
We omit this section.
10.  Process Control Monitor Chip
We omit this section.
11.  Appendices
11.1.  Impact of Transient Currents On Metal Width Rules
[The following is quoted from VTI's rules, with our comments added in square brackets.]
High performance output buffers designed in 2 to 3 micron CMOS require special considerations.  Each buffer is typically capable of sinking and sourcing up to 20 mA, when first turning on into a 50 to 150 pF load.  The effect of this on internal GRD and VCC busses is to raise and lower the voltages of these busses respectively.  The worst case is encountered in groups of eight or more that synchronously switch, as do data/address busses.  These can easily result in GRD "NOISE" that exceed normal TTL VCL limits.  While this may not interfere with internal CMOS operation on the buffers themselves, it will almost certainly cause problems on all other outpus on the chip that are trying to hold a TTL low output.....i.e, a one volt, ten nanosecond spike appears as a switching transient.
Design rule minimum metal widths of 1 mA/micron [0.75 mA/micron for metal2, 0.5 mA/micron for metal1] do not then adequately address this problem.  This rule only accounts for DC currents, after the transients have disappeared.
These CMOS devices have, in many designs, achieved the performance of TTL, and the bussing must be appropriately increased.  TTL die sizes, and corresponding length of metal lines back to the ground/VCC pads are smaller than most, if not all the CMOS VLSI devices addressed by these design rules.
Solutions:
First calculate the transient currents....use I=C*(dV/dT) for your buffers.
Typical: 50 E-12*(5/15 E-9) = 17 mA per buffer.
Next use 0.03 ohms/sq to get back to the bonding pad.  [ICL's figures are 0.065 ohms/sq typ. for metal1 and 0.042 typ. for metal2.  VTI's figures are 0.03 ohms/sq max for both metal1 and metal2.]  The bond wire can be estimated at 0.5 ohms.  If the buffers are at the opposite end of the chip...away from the ground pad...and the metal width is 5 mils, with a 200 mil bus run, there are 1.2 ohms in the metal bus.  With eight buffers AS ABOVE, we have 160 mV at the PAD, appearing on all other outputs when these eight buffers switch.
Understanding the size of the transients, you can take several actions to reduce the size of the problem.
1.  Use down bonds near, preferable in the middle of synchronous busses.  Allowable downbond locations are package dependent, and will require additional information.  See Section 7.3., or consult the factory.
2.  Increase metal width.
3.  Put GRD very near the outputs....not at the opposite end of the chip.
4.  Do not "overkill or overdesign" outputs.  Only design for the speed required by your application.
5.  Consult the factory (design center) for help if the above cannot solve the problem for the calculations of transient currents as required by your design.
11.2.  Terminology
11.2.1.  Overlap
Some design rules specify that one material must overlap another by at least a certain distance.  In this document, we use the term "overlap" in an unusual way, which is explained in this section.
Suppose the rule says that A must overlap B by at least N lambda.  The rule means that:
o  The bottom edge of A must be at least N lambda below the top edge of B; AND
o  The top edge of A must be at least N lambda above the bottom edge of B; AND
o  The left edge of A must be at least N lambda to the left of the right edge of B; AND
o  The right edge of A must be at least N lambda to the right of the left edge of B.
In particular, it doesn't mean that A and B are required to have a width of at least N lambda.  (It does, however, turn out to be the case that the sum of the widths of A and B must be at least 2*N lambda.)
For example, design rule 6.3.8. says that N+ guard ring must overlap (drawn) N-well by at least 5 lambda.  But the N+ guard ring is permitted to be only 2 lambda wide.  N-well, however, must be at least 12 lambda wide.
Another way of expressing rule 6.3.8. is that if we construct a shape which is undersized from (drawn) N-well by 5 lambda, then the N+ guard ring should still touch or overlap (in the usual sense) that shape.  This version of the rule may be more intuitive, but it takes longer to say.
11.2.2.  Surround
Some other design rules specify that one material must surround another by at least a certain distance.  Suppose a rule says that A must surround B by at least N lambda.  The rule means that:
o  The bottom edge of A must be at least N lambda below the bottom edge of B; AND
o  The top edge of A must be at least N lambda above the top edge of B; AND
o  The left edge of A must be at least N lambda to the left of the left edge of B; AND
o  The right edge of A must be at least N lambda to the right of the right edge of B.
In particular, note that surround and overlap mean different things.
11.3.  N-Well Rules
In this section, we attempt to explain why it is that all of the rules pertaining to the N-well seem to be so terribly complicated.
11.3.1.  What Does Drawn N-Well Mean?
First, there is the question of where the N-well is drawn.  These design rules are written to pertain to features as they are drawn, assuming the N-well is drawn where ChipNDale, Xerox PARC's integrated circuit layout software, would draw it, and where Spinifex, Xerox PARC's integrated circuit design rule checking software, would check for it.  When P-channel transistors and N-channel transistors are separated by the minimum spacing of 10 lambda (see Section 6.3.12.), ChipNDale and Spinifex would like to see the N-well drawn to surround P+ by 5 lambda and avoid N+ by 5 lambda.  The drawn location of the N-well is conventional and doesn't necessarily correspond to any physical thing related to N-well.
VTI's rules assume that N-well is drawn where the N-well dopant is implanted.  In VTI's case, the dopant is implanted through an oxide cut.  Subsequently, during "drive-in," this dopant diffuses vertically into the chip to form the N-well.  It also diffuses laterally, about 3 microns on each side, so that the final N-well electrical boundary is 3 microns per side oversized, compared to the VTI-drawn location.
ICL's rules assume that N-well is drawn where the final electrical boundary is located.  Like VTI, the final electrical boundary is 3 microns oversized from the area into which dopant is implanted.
In going from one set of rules to another, these differences in the drawing of N-well must be taken into account.
11.3.2.  Where Should the N-Well Electrical Boundary Be?
Normally, ICL would like to see the N-well electrical boundary 4 lambda from P+ and 6 lambda from N+.  They believe that it is not critical to locate the boundary exactly there, for two-micron technology, but that for 1.2-micron technology it may become more critical.
VTI's official rules require a 12-lambda space between P-channel transistors in the N-well and N-channel transistors outside the N-well.  The rules further require the N-well edge to be drawn 5 lambda from P+ and 7 lambda from N+.  That means VTI wants the N-well electrical boundary to be 8 lambda from P+ and 4 lambda from N+.
Because we have a requirement for a more aggresive spacing, and because ICL and VTI tests indicate that it's possible to have a smaller spacing, VTI has agreed to support a 10-lambda spacing.  To accomplish the 10-lambda P+ to N+ spacing, VTI at first requested that the electrical boundary be placed 8 lambda from P+ and 2 lambda from N+.  However, ICL was worried that the spacing between N-well and N+ was small enough that leakage between the two could occur due to short channel effects.
On November 26, 1985, ICL and VTI people met to discuss this issue, and as a result, VTI agreed that the electrical boundary could be placed 7 lambda from P+ and 3 lambda from N+.  ICL's Richard Bruce then indicated that ICL might be able to live with this location of the N-well electrical boundary, but that it would be nice to verify this with some tests.  These tests (or some of them) were put on run MPC5NA, which closed December 2, 1985, or thereabouts.  So the results should be available sometime around February of 1986.
It would be very desirable to have ICL and VTI agree on where to put the N-well electrical boundary for two reasons.  First, it would be possible for ICL and VTI to use the same N-well and P Field Implant masks, which would save on mask costs.  Second, in integrated circuit layouts, no space would have to be wasted to take into account both possible locations of the N-well electrical boundary.
In summary, VTI's N-well electrical boundary is 2 lambda oversized from drawn, and, for the moment, ICL's N-well electrical boundary is 1 lambda undersized from drawn, although that location could change, depending on the outcome of some tests in progress.
11.3.3.  Inferring Rules
In many cases, VTI has a design rule and ICL has no corresponding design rule.  In general, we assume that this design rule document should have a rule that captures the spirit of the VTI rule but is also applicable to the ICL context.
Although this approach seems to make sense, sometimes it leads to a result which is difficult to accept.  For example, consider Section 6.3.6. (or Section 7.5.2.2.). VTI's rule, translated to our drawing conventions, requires N-well to surround N+ contact by 4 lambda.  ICL has no explicit rule, but clearly depends on some kind of implicit rule.  Since ICL's N-well electrical boundary is 3 lambda undersized from VTI's N-well boundary, the analogous rule would be that N-well must surround N+ by 7 lamba.  This is a rather ugly rule.  It says that N-well must surround N+ by a larger amount than it must surround P+.  Should we adopt the 7-lambda rule?  Or should we adopt the 4-lambda rule and not worry about the ICL case?
¦/Ivy/Hoel/Dragon/Foundry/DragonCMOSDesignRulesC.tioga
Jeff Hoel, January 26, 1986 12:01:41 pm PST

Copyright c 1986 by Xerox Corporation.  All rights reserved.
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