Jeff Hoel March 14, 1987
Introduction
The advisory comments in this document are indended as a supplement to the VTI design rules, which we have adopted as the rules for designing Dragon chips (except for EU and IFU). Following only the VTI rules should be good enough to assure that a chip can be fabricated at VTI using any process which the rules explicitly support. Advisory comments a) clarify the official VTI rules, b) predict likely changes to VTI rules, c) make it more likely that a design can be fabricated using another process, either at VTI or elsewhere, etc. Designers are free to observe advisory comments or not. (But designers are required to track all changes to VTI's design rules as they occur.)
Advisory Comments
Via Flatness: We recommend that a) diffusion avoid via on field oxide by 2l, and that b) diffusion surround via on diffusion by 2l. Given the possibility of mask misalignment during fabrication, this follows logically from VTI's rule 6.7.1., which in effect requires a via to be entirely on something flat (field oxide, diffusion, or poly). VTI used to have official rules like these and still advises observing them.
Angle Transistors: We recommend that designs not use transistors with 90-degree bends in their gates. It is difficult to predict the effective width of these transistors, due to current crowding effects. Moreover, higher electric fields at the corners might cause problems with hot electrons or punchthrough, particularly for sub-2-micron geometries. Although the VTI design rules do not explicitly forbid these transistors, VTI says they'd rather not see them for the 1.6m process.
Metal1 Width: We recommend that designers draw metal1 at least 3l wide. VTI has indicated that until their 1.6m process is fully characterized, the possibility exists that some design rules may have to be made more conservative, although they didn't say which ones. For the 1.6m process, VTI is switching to a new metal system (very similar to the one ICL used for their 2.0m process). VTI says that because of this the metal design rules are perhaps more likely to change than most.
Vias on Poly: We recommend that designers not put vias on poly. VTI's 3l surround rule 6.7.7. is so large that it would rarely be advantageous to use a via on poly to achieve optimal packing density. VTI agrees, and has discouraged their use. NCR, a possible second source candidate, forbids them.
Atomic Objects for Cuts and Vias: We recommend that designers use the existing ChipNDale atomic objects for cuts and vias of non-minimum size, even though they have larger surrounds than are required by the VTI design rules. Also, we recommend using the existing ChipNDale atomic objects for split cuts, even though they can be only one size. The reason is to avoid introducing extra complexity.
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY