Jeff Hoel
This document summarizes the CMOS design rules used by the Dragon project for laying out the interior parts of Dragon chips. (The interior of a chip is defined to be that portion of the chip in which latch-up triggering events cannot occur.) A more complete set of design rules is specified in reference [1].
Diffusion
Diffusion Minimum Width: 2 lambda
Diffusion Minimum Spacing: 3.5 lambda
Minimum Spacing between P+ in N-well and N+ outside N-well: 10 lambda
Diffusion Extends Beyond Gate: 3 lambda
(Minimum Diffusion Width Between Poly and Field Oxide)
Gate Avoids Well/Substrate Contact Diffusion: 3 lambda
(Minimum Diffusion Width Between Poly and Opposite Type Diffusion)
Poly
Poly Minimum Width: 2 lamba
Poly Minimum Spacing: 2.5 lambda
Poly Avoids Unrelated Diffusion: 1 lambda
Poly Gate Extension: 2 lambda
Poly Gate Minimum Width: 3 lambda (Exception: if uniformity and perfomance are not important, transistor gates may be 2 lambda wide.)
Cut
Cut Minimum Size: 2 x 2 lambda (Exception: Split Contact Cut: 2 x 6 lambda.)
Cut Maximum Size: 5 x 5 lambda (Exception: Split Contact Cut: 2 x 6 lambda.)
Cut Minimum Spacing: 3 lambda
Cut (Contact to Diffusion) Avoids Poly Gate: 2 lambda if cut is minimum size; 3 lambda otherwise
Cut (Contact to Poly) Avoids Diffusion: 2 lambda
Diffusion Surrounds Cut: 1 lambda if cut is minimum size; 2 lambda otherwise
Poly Surrounds Cut: 1 lambda if cut is minimum size; 2 lambda otherwise
Metal1
Metal1 Minimum Width: 3 lambda
Metal1 Minimum Spacing: 3 lambda
Metal1 Surrounds Cut: 1 lambda if cut is minimum size; 2 lambda otherwise
Metal1 Current Limit: 0.5 mA/micron of width
Via
Via Minimum Size: 2 x 2 lambda
Via Maximum Size: 5 x 5 lambda
Via Minimum Spacing: 4 lambda
Metal1 Surrounds Via: 1 lambda if via is minimum size; 2 lambda otherwise
Via Avoids Cut (Contact to Poly): 3 lambda
Via Avoids Cut (Contact to Diffusion): 2 lambda
Flatness:
Via on Field Oxide Avoids Diffusion: 2 lambda (advisory)
Via on Field Oxide Avoids Poly: 2 lambda
Poly Surrounds Via on Poly: 3 lambda
Diffusion Surrounds Via on Diffusion: 2 lambda (advisory)
Via Current Limit: 0.07 mA/micron of perimeter
Metal2
Metal2 Minimum Width: 4 lambda
Metal2 Minimum Spacing: 4 lambda
Metal2 Surrounds Via: 1 lambda if via is minimum size; 2 lambda otherwise
Metal2 Current Limit: 0.75 mA/micron of width
N-Well
N-Well Minimum Width: 12 lambda
N-Well Minimum Spacing: 12 lambda
N-Well Surrounds P+ Diffusion: 5 lambda
Substrate (i.e., absence of N-Well) Surrounds N+ Diffusion: 5 lambda
N-Well Surrounds N+ Well Contact Diffusion: 4 lambda
Substrate (i.e., absence of N-Well) Surrounds P+ Substrate Contact Diffusion: 4 lambda
Well Contact Maximum Spacing: 75 microns
Substrate Contact Maximum Spacing: 75 microns (Note: this rule applies only within the "virtual P-well" portion of the substrate, i.e., close to N-channel transistors, where the P-well would be in P-well or twin-well technologies. For example, it does not apply to areas used only for routing metal traces.)
Maximum Spacing of Well Contact from P+ Source at VDD: 30 microns (Note: use a split contact whenever possible.)
Maximum Spacing of Substrate Contact from N+ Source at VSS: 30 microns (Note: use a split contact whenever possible.)
Other
Buried Contacts are not permitted.
Butting Contacts (between poly and diffusion) are not permitted.
Angle Transistors are explicitly permitted.
All geometries must fall on a half-lambda grid.
References
[1] Dragon CMOS Design Rules; Jeff Hoel; Xerox internal document /Ivy/Hoel/Dragon/Foundry/DragonCMOSDesignRulesB.tioga, revision B, December **, 1985.