Figure 2. D Bus TimingFigure 2a. Hold TimingAll components do not update their state during this cycle.processor: DHoldAB _ TRUEAll components continue execution normally during this cycle3124All components continue execution normally during this cycle; processor: DHoldAB _ FALSE42135The selected component prepares itself for execution during this cycle; processor: DExecuteAB _ FALSEAll components prepare to resume execution.First cycle that execution may resume.The content of the shift register is replaced. First cycle that DHold may fall.312selected component: DDataOutAB changesprocessor: DShiftAB _ TRUE; selected component: sample DDataInprocessor: DShiftAB _ FALSE; selected component: insert bit into shift register, extract bit that falls out the endFigure 2b. Execute TimingFigure 2c. Shift Timingprocessor: {DExecuteAB _ TRUE; DHoldAB must be true by the end of this cycle}:K VtR; VV VPJ<pR_VTP& VtU&Xp>^BE @<% VtBe V>+ V