InternalMemo1XEROXToFromDragonCoreRickBarthPARC-CSLSubjectDateMBusCompatibilityNovember19,1984IntroductionLong,long,agoandfar,far,away,sayabout400miles,ChuckThacker,RonRider,SteveDashiellandGodknowswhoelsesatdownanddecidedwhatthemainbus,calledtheMbus,shouldlooklikeforanewmemorysystem.ForavarietyofreasonscommunicationsbetweentheDragondesigncrewandthefolksdownsouthbrokedownoverthelastcoupleofyearsandthedecisionsregardingthecommonbusfellbythewayside.SometimetowardstheendofAugustofthisyearRonRidercamecruisingbyandEdMcCreight,CarlBlackandIhadalittlemeetingwithhimwherewetalkedabouthowsimiliarourmainmemorybuseswereand,gosh,wouldn'titbeniceiftheywerethesame.Therehavebeenanumberofphonecalls,wemadeavisittoElSegundo,andanumberofmessageshavebeentransmittedsincethen.Thismemoisanattempttowritedownthestateofcurrentdesigns,futuredesignsthatarecontemplatedwhichdependoncurrentdesigns,differentoptionsfromwhichwecanchoose,theimpactoftheoptionsuponthedesigns,specificallyDragon,andtocometosomesensibleconclusionaboutwhatweshoulddo.CurrentDesignsESSThecurrentESSdesignhasonlyonecustompartthatdependsontheMbusprotocol.ItisacacheandwillbereferredtoastheESScache.ThespecificMbustowhichanESScachemaybeattachedisreferredtoastheESSMbus.TheESScacheisbeingusedtoconnecta8086stylebustotheMbus.Ithasasmallamountofcacheddata,about16quadwords,andhasfacilitiesformailboxesandstreamoperations.Ithas24bitreal,andvirtualaddressfieldsalthoughtheprotocolallowsspacefor31bitvirtualaddressesand28bitrealaddresses.Theprotocolhas3freecommands,oneofwhichisactuallyusedinternallybythecache,leaving2freecommandsforexpansion.TheESScachedoesnothaveanyflowcontrolledI/Ooperations.ThismakesconnectingthesynchronousMbustoanasynchronousbussuchastheVMEbusmoredifficult.ItalsopreventsthemapprocessorfromusingtheMbusduringmapoperationstherebyforcingmapmemoryaccessestotakeadifferentroute.Thepf]qfCNrf{sb ]b 2Pq`d]`d2P5^2P67sT]T2PqS']  S'2P9`;tI:] uE(W!"#&I*2,03B7L;ADD](z!$>(p+c.036r;>AB]J?vBBtueBB@#&){+,/57:=4>[B@]6 g%(+-%1o47b9=@?N]V.U!P%'+*-0\6E<|>=]]Y;+"'$&+g-%/259=kB9]A { $N'(*+/4P7g:<>Q@u7]Pf_#),0<3]7<>6@8C865]o#"%)+*V/1?5{8; >?B4],5"B#)-0z 7;,2hk$&*P.J0496!;@u0k]Q@ $^(-/49?.]"v$)e+"-2h68c= -]l s$)1 037@9g=t&]vw#/]u#7%(+0]3L6&;=@B9]Y"%~',.0Zv29936u9O99:=B]"s%y'l,.W35K6v9]:P<>ku@\A]d= "'(,@/~2!36I81;=B?@C]zD W$J&A).G13 9 ;ZA] " "$'*n.372<?+]1gDZ#),i.G0\3 9<B$M]!n%',@/ 57:W>Cd]*L * #f&)O,j 25 =E@`] e "$')G+N 369;>,B ] n%(#+`15!8;q=n@( 4]h $'-2+367=eA9TVm$InternalMemo2I/Oaddressspacedoesnothavelargecontiguoussectionsandislimitedtoatotalofnomorethan25bitsbecause4bitsareusedforthecommandfieldandatleast3bitshavebeenremovedtoease8086compatibility.ThisdoesnotallowaddressinglargeframebuffersintheI/Ospace.Provisionsformultipleaddressspacesarenotyetimplementedandtheproposedchangetoallowforthemdoesnotcleanlyimplementtherequiredoperations.EDiscurrentlyawaitingsecondsilicononthischip.Firstsiliconshowedgreatpromise.AnumberofI/Ocontrollers,includingdiskandEthernetcontrollers,havebeenorarebeingconstructedbasedonthecapabilitiesoftheESScache.Memorycontrollershavealsobeenbuilttothisspecification.DragonThereisadesignfortheDragoncachethathasexecutedeachtransactionontheMbusandallofthecommandsonthePbus.TheexecutionwasdrivenbyablackboxRosemarytestprogram.ThelevelofdescriptionintheRosemarycodeisslightlyabovethatoftransistors.Thelayoutforanentryofthecachehasbeendone,althoughthefirstpassatthecontrollogicforanentryrequirestoomuchspaceandsoitwillhavetoberedone.SomepreliminarylayoutoftheCAMandRAMdrivershasbeendonebutthedesignhaschangedsomuchsincethesewerelayedoutthatatbesttheyserveasguidelinestohowbigtheseblocksmightbe.Basicallyaveryfirmspecificationforthecircuitdesignandlayoutportionsofthedesignprocessisinhand.About6monthsofworkremainspriortosubmittingfirstmasksforprocessing.ModificationsthatwillbemadetotheDragoncacheBytewriteenablepinswillbeaddedtothecache.Abusmodepinthatcausestheparitybitofawordbeingwrittentobecalculatedinternallywillbeadded.ThesepinswillbeaddedtothedesignregardlessofwhetherornottheentireDragoncacheisredesigned.Theyallowforattaching68020and80186processorstotheDragoncache.AsmallpileofSSIandMSIcruftwillberequiredbetweenthecacheandsuchforeignprocessorsbutimplementationwillbestraightforward.Iplantoattach68020processorstoacompleteDragonmemorysysteminordertotestitindependentlyoftheDragonprocessor.Ifsomeoneweretositdownandplaywiththe68020and80186processorinterfacesenoughthatwecouldbereasonablysureofgettingtheinterfacelogicrightthereisplentyofsiliconareatoembedtheinterfacefortheDragon,80186and68020allononedieandusestrappinstoselectwhichprocessorisactuallyattached.Currentlythereisnowaytodetectwhenanillegalmemoryreferenceismade.Thecontrollersineverybusmasterwillbemodifiedtodetectwhenthecommandwiresonthebushavenotbeendriventoavaluedifferentthanthevaluewithwhichthebusmasterstartedatransaction.Abusmasterthatdetectsthisconditionmustraiseanerrorandreleasethebus.Thecachecanhandlethiscleanlybycausingitsprocessortotrap.I/Ocontrollersmightsetanerrorflag.ThemapprocessorcouldsetanerrorflagandreturnanerrorconditionastheresultoftheIOReadorIOWritethatstartedthemapprocessor.ThereareafewinconsistenciesbetweenthecurrentMbusspecificationandtheimplementationthatmustbecleanedup.Reasonstoredesignthecachepf]qfCNub2]4) $"%)h 0c58Q9>@?As`] b%&)]+.1-39=!?As^]|7~!"%( 147:B= ]<]n!{$HZ "&*-/o1 9<]>Y]\!#$S&+p2U4:D V #V',-..047<6A&T]P": )A/@24:K ARSO]{ #'),0 3K57b:Z>Q] !g4!$&)( wNX]uK 4R!$)'-/2p8?; BIb]?!(*,s-1M4,:g=AmCoG]_ '*g-/ 68`:ARF] M '*.1!368}:>A<Dl]P5 #%()-0248>0@B]! "$*F.% 59;=AA]Qj#K%(>,/46Z::=AH?v]'fk"&D( .036)9>9BQ=]Xw &(+J/36:@pB9<']_Y!%&+-n059X: A:]t v70] D!$&O(-u3G" $&*,[.3J47^;,=@_29]^F!V%P*2,./ 4 ;#=@0]"?$(&+L 139d;c>@.]kF #'6*-:31769> -C]|> $z':(+.[1479?*+]" )U+ 58:)]g3C; %'(.39=?4B(M]~  x"( /D06:0;=A&]1="O&- 38<>B$] BF !$)-0z459;?B#W]V L"(,.2469;>A1!]V#%R*h4_V!]$6%)-/39?@]@  #('*Y,T2;38;>8]!2${(*Q+g.479=@>][P ~ (^),038h;A1]!)#&)-047:;=B]ep &(*,%. 1p47:@H]]1!!#&,.04~68^=y? ]+! %C(%-095%7"9 A~]  i#%*v /]G TVm$InternalMemo3RegardlessofwhichMbusprotocolisusedtherearesomereasonstoredesignthecache.ThemostimportantreasonistomaketheRAMstatic.DynamicRAMisaholdoverfromThacker'sdesignthatIneverreallythoughtallthewaythrough.Theproblemwithitisthatwecannotcalculatetheerrorratethatwillbeintroducedbyalphaparticlehits.Wehavetobuildthecellandseewhattheerrorrateis.Waitinguntilwehavebuiltthecacheandembeddeditinthesystemtofindoutiftheerrorrateisacceptableseemslikearecipefordisaster.AsingleportstaticRAMwillhaveaboutthesameareaasthedualportdynamicRAMinthecurrentdesign.IcangothroughreasonablebandwidthargumentswhichshowthatadualportedRAMisnotneededfortheDragonanyway.Somethoughtshouldbegiventotheamountofbandwidtha68020or80186willrequireifattachingthoseprocessorsinanoptimalmannerisfelttobeveryimportant.Anotherreasontoredesignthecacheistoremovesomeofthecomplexityfromthebuscontroller.IamstilladaptingtothedelaycharacteristicsofduallayermetalandIputsomecomplexityintobuildingafastcontrollerthatcouldprobablybeeliminatedthroughjudicioususeofsecondlevelmetal.FinallyIhavesomeideasabouthowtodothedesignusingabettermethodology.Thisisnotaverycompellingargumentfromaprojectmanagementpointofviewexceptthatitkeepsmeinterestedindesigningthebeast.Designingitforthefourthtimewithchangestothespecificationsbutnottothemethodologyisboring.Changingbothcouldbeatleastsomewhatinteresting.Redesigningthecache,assumingthatstrictcompatibilitywiththeESSMbusisnotrequired,thatthedesignmethodologyisnotchanged,andthatIdotheredesign,willaddabout3monthstothedesignschedule,changingitfrom6monthsto9monthsuntilfirstmasks.FutureDesignsCWorkstationTheCworkstation,which,lestanyonebecomeconfused,hasnothingtodowiththeCprogramminglanguage,isplannedtobeintroducedbyXeroxinearly1987.TherequirementsthatIhaveseenforitspecifythatitbeamultiprocessorandallowforeignprocessorstobeattachedtoit.ThenotionisthatsomenumberofenhancedMesaprocessorswillbethemaincomputingenginesinthismachine.Theactualamountofmanpowerworkingonitrightnowisverysmall.Duringthesummerof1985itisexpectedthatthemanpowerwillrampup.SteveDashielltoldmethattheywouldliketomovetheI/OcontrollersfromtheESSdesigndirectlyintotheCworkstation.TheyexpecttodesignaprocessorcacheinCMOSsothatitwillperformadequatelywith16MHzprocessors.TheyrealizethattheESSMbusprotocolisinadequatefortheCworkstationbutbelievethattheI/Ocontrollerscanstillbesalvaged,atleasttemporarily.IhavetroublebelievingthattheI/Ocontrollersshouldbesalvagedforaproductwhichisslatedtocomeoutsometimeafter1Q1987.Morecosteffectivesolutionsarebecomingavailablefor2ofthekeycontrollers,diskandEthernet,andanewworkstationshouldbedesignedtotakeadvantageofthem.Itisnotclearhowrealthescheduleortheproposeddesignareatthispoint.ItisespeciallyinterestingtonotethatnoneoftheSBU'shavesignedupforthispf]qfCNub2  "%**+/525 8=u? `]^!%'(,/,357=ACo\i]b $'y(n,$/469;AZ]J!&+.14L79; BY] 3"$v(*L,/e1478:=D?bWs];#W&,./26z8!;=v>A'U]>  #$)+^1m37":;=AT$]!#A%(+1k5_79>SCR}]; ")048;<@3P]J- 6"'-j1A6e:<@B9O.]k& 0$)%),1a287:: A2Id]2 ,% h"(*,,{08:m=w@G]6` "%+t,/w 58<BF] !Y#6%'d+/<C #_')+v-R/37-8-; A] $*N-/3 ;?A^@L]Ze %'-/4-:;>@_>]D"x +3.025 >?<] ".%S+ : w"(+/ 7s:=@B8]!m% .s028;>?B973]W &!G&'*.B4-9;:>?5] @*qIt.]w+] u(QR $R&+s0u68=?A~&]T $%*,. 57;=@%]! _ #@&F(o).902545( >M@#[] & %k')+01u407<>n!]  # &-24a7=@ ]`$&'h*-/26;D=Be]e!"O)+/]S :"%y(,/1J57:` A2B]# ##%n& /S27@8=R>]5| V!$n) 0359 A]y"+'( /2246 =k?L]E #'%'-/2 ;MNV]G"U ),/58:=0 ]4"-(*] 4' +"%g+ ,/i5z9?AG]<]Y  f&)':).0?3L6y >z tV]wSP] #H -uPt#$'$ .V 58;>@CNZ]!"%+*-24D6 =L]| "')(,/M3W 9;W= K ]uHX"%[)s-.24:;>{@4F] _"(+.2"369<>U@BEB]J!V#(,[-17:1=[AC]oWZ!$'-.206>7;A~A]C`  t#%(-136=9=.>A<@L]v#8'`),1 4>69 A>]/n!&),K0o35;> @B<] 8$6&(L*023 N !({./2:5:=@9]$+-1357; ?AS8]O #~%H'+.1U379@;B6`]I"" +@.13783459F;B9*]wj!g#%~*- 45;BE)%] !-&].$&t025d7m<?(A%] !#' ,/&16;?W#[] ]K 'I)-/47: @!] !$6'=)%+1~3829]K #k'*,.~4Z67 ?Bo]{ %q(,*W.'263 p ]j &** 03F6<7=(As 4]%w$e& /1o5T8>A ]h"x%*R+-1 49;>@ TVm$InternalMemo5alloftheworkandthereisamuchlessclearpathfromresearchtoproduct.ConsideringtheDragonasanisolatedprojectIbelievethatthisroutewillgiveusworkingDragonsfasterthantryingtobecompatiblewiththeESSbusbutispotentiallyslowerthanthenextalternative.CooperativelydesignanewbusandthechipsthatgoonitThisoptiongivesustheopportunitytocleanupallthewartsintheESSMbusdesignthatwehavediscoveredsofar.Withthiscooperativeoptionwehavelesstimetonoticenewwartsbeforetheysolidify.TherestillremainstimebetweennowandwhentheCworkstationisfullystaffedtofinishthearchitecturedowntoquitedetailedsimulations.IthinkthismaybethefastestmethodofproducingbothworkingDragonsandworkingCworkstations.ConclusionsThemajormotivationsforbecomingcompatiblewithanEDMbusaretoeliminateneedlessreplicationofeffortinresearchanddevelopmentandenhancetheexchangeofideasandresultsbetweenresearchanddevelopment.Weshouldpursuethesegoals.WeshouldnotattempttodosobybecomingcompatiblewiththeESSdesignbecauseofthedeficienciesintheprotocoloutlinedearlier.ConvergenceoftheDragonandEDMbusesshouldoccurintheCworkstation.TheI/OcontrollerissueshouldberesolvedbyeitherredesigningtheI/Ocontrollersordesigningagatearraythattranslatesbetweenthenewandoldbuses.JointdesignofacacheforDragonandtheCworkstationshouldbeexplored.Technicalexchangeofportionsofthedesignsshouldoccurevenifindependentdesigneffortsarepursued.pf]qfCNub2]4"$q%),0l37=,?`]   "R$O)f./%369l=?B^] $J(*, 4*7:;=@aC-]<] ,{"% wY] 2g"3$'S)-902 4uV+w " *k, /13w59Y:=K@6BT]F %-' *;-0 7BSP]u! $'-v1k39<4AQ]' #$}',3-14 ;?aAP] E $R'&*\,/3s8:A]NZ]8$F% tG] uDn/] "%s+ 3@68;~=@_BB]~ $%)+1*4 5]_ "'+/20 9=BE3]GTVm$a TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMANY HELVETICALOGO HELVETICA HELVETICA   )/j/20۪n[]<>MBusAnalysis.tioga$Monday, December 3, 1984 3:55 pm PST