DRAGON Instruction Set Summary
Name form # Description
ADD OI 1 [S-1]←[S]+[S-1]+carry; carry ← 0; S←S-1; trap on overflow
ADDB OB 1 [S]←[S]+AlphaZ+carry; carry ← 0; trap on overflow
ADDDB ODB 1 [S]←[S]+AlphaBetaZ+carry; carry ← 0; trap on overflow
ADDQB OQB 1 [S]←[S]+AlphaBetaGammaDelta+carry; carry ← 0; trap on overflow
AL OB 1 L←L+Alpha
ALS OB 1 L←S+Alpha
AND OI 1 [S-1]←[S] AND [S-1]; S←S-1
AS OB 1 S←S+Alpha
ASL OB 1 S←L+Alpha
BC OI 1 trap if [S-1]>=[S] (unsigned); S←S-1
CST OB 1 [S+1]𡤌Store[ptr: [S-2]+AlphaZ, new: [S-1], old: [S]]; S←S+1
DFC OQB 1 call proc at AlphaBetaGammaDelta
DIS OI 1 S←S-1
DUP OI 1 [S+1]←[S]; S←S+1
EXDIS OI 1 [S-1]←[S]; S←S-1
FSDB ODB 1 Field𡤊lphaBeta+[S]; S←S-1
JB OB 1 PC←PC+Alpha
JDB ODB 1 PC←PC+AlphaBetaS
JEBBj JBB 2 AlphaZ = [S] => PC←PC+BetaS; S←S-1
JQB OQB 1 PC𡤊lphaBetaGammaDelta
Jn O* 4 Noop of length 1, 2, 3, or 5 bytes (used as jump)
JNEBBj JBB 2 AlphaZ # [S] => PC←PC+BetaS; S←S-1
JSD OI 1 PC←[S]; S←S-1
JSR OI 1 PC←PC+[S]; S←S-1
IOD ODB 1 IsRead[BetaZ] => [S+1]←PRead[AlphaZ, BetaZ]; S←S+1
IsWrite[BetaZ] => PWrite[AlphaZ, BetaZ, [S]]; S←S-1
ION ODB 1 IsRead[BetaZ] => [S+1]←PRead[AlphaZ, BetaZ]
IsWrite[BetaZ] => PWrite[AlphaZ, BetaZ, [S]]
IODA ODB 1 IsRead[BetaZ] => [S]←PRead[AlphaZ+[S], BetaZ]
IsWrite[BetaZ] => PWrite[AlphaZ+[S], BetaZ, [S-1]]; S←S-2
KFC OI 1 PC ← InstTrap[KFC]; kernel mode; disable traps
LCn OI 12 [S+1]𡤌onstants[n]; S←S+1
LFC ODB 1 call proc at PC+AlphaBetaS
LGF ODB 1 [S+1]←(AuxRegs[0]+AlphaBetaZ)^; S←S+1
LIB OB 1 [S+1]𡤊lphaZ; S←S+1
LIDB ODB 1 [S+1]𡤊lphaBetaZ; S←S+1
LIP OB 1 [S+1]←PReg[Alpha]; S←S+1
LIQB OQB 1 [S+1]𡤊lphaBetaGammaDelta; S←S+1
LRIn LRB 16 [S+1]←([L+n]+AlphaZ)^; S←S+1
LRn LR 16 [S+1]←[L+n]; S←S+1
OR OI 1 [S-1]←[S] OR [S-1]; S←S-1
PSB OB 1 ([S-1]+AlphaZ)^←[S]; S←S-1
QADD QR 1 Rc←Ra+Rb+carry; carry𡤀 trap on overflow
QAND QR 1 Rc←Ra AND Rb
QBC QR 1 trap if Ra >= Rb (unsigned); Rc←Ra
QLADD QR 1 Rc←Ra+Rb; carry𡤀 trap on Lisp NaN
QLSUB QR 1 Rc←Ra-Rb; carry𡤀 trap on Lisp NaN
QOR QR 1 Rc←Ra OR Rb
QRX QR 1 Rc←(Ra+Rb)^
QSUB QR 1 Rc←Ra-Rb-carry; carry𡤀 trap on overflow
RADD RR 1 Rc←Ra+Rb+carry; carry𡤀 trap on overflow
RAI LRRB 1 [L+BetaL]←(AuxRegs[BetaR]+AlphaZ)^
RAND RR 1 Rc←Ra AND Rb
RB OB 1 [S]←([S]+AlphaZ)^
RBC RR 1 trap if Ra >= Rb (unsigned); Rc←Ra
RET OB 1 S←L+Alpha; return
RETN OI 1 return (no S change)
RFU RR 1 Rc𡤏ieldUnit[Ra,Rb,Field]
RJEBj RJB 2 Rs=Rb => PC←PC+BetaS
RJGBj RJB 2 Rs>Rb => PC←PC+BetaS; signed comparison
RJGEBj RJB 2 Rs>=Rb => PC←PC+BetaS; signed comparison
RJLBj RJB 2 Rs<Rb => PC←PC+BetaS; signed comparison
RJLEBj RJB 2 Rs<=Rb => PC←PC+BetaS; signed comparison
RJNEBj RJB 2 Rs#Rb => PC←PC+BetaS
RLADD RR 1 Rc←Ra+Rb; carry𡤀 trap on Lisp NaN
RLSUB RR 1 Rc←Ra-Rb; carry𡤀 trap on Lisp NaN
ROR RR 1 Rc←Ra OR Rb
RRI LRRB 1 [L+BetaL]←([L+BetaR]+AlphaZ)^
RRX RR 1 Rc←(Ra+Rb)^
RSB OB 1 [S+1]←([S]+AlphaZ)^; S←S+1
RSUB RR 1 Rc←Ra-Rb-carry; carry𡤀 trap on overflow
RUADD RR 1 Rc←Ra+Rb+carry; set carry
RUSUB RR 1 Rc←Ra-Rb-carry; set carry
RVADD RR 1 Rc←Ra+Rb
RVSUB RR 1 Rc←Ra-Rb
RX OI 1 [S-1]←([S-1]+[S])^; S←S-1
RXOR RR 1 Rc←Ra XOR Rb
SFC OI 1 call proc at [S]; S←S-1
SFCI OI 1 call proc at ([S])^
SHDL ODB 1 [S-1]𡤏ieldUnit[[S-1],[S],AlphaBeta]; S←S-1
SHDR ODB 1 [S-1]𡤏ieldUnit[[S],[S-1],AlphaBeta]; S←S-1
SHL ODB 1 [S]𡤏ieldUnit[[S],0,AlphaBeta]
SHR ODB 1 [S]𡤏ieldUnit[[S],[S],AlphaBeta]
SIP OB 1 PReg[Alpha]←[S]; S←S-1; {kernel}
SRIn LRB 16 ([L+n]+AlphaZ)^←[S]; S←S-1
SRn LR 16 [L+n]←[S]; S←S-1
SUB OI 1 [S-1]←[S-1]-[S]-carry; S←S-1; trap on overflow
SUBB OB 1 [S]←[S]-AlphaZ-carry; trap on overflow
SUBDB ODB 1 [S]←[S]-AlphaBetaZ-carry; trap on overflow
SUBQB ODB 1 [S]←[S]-AlphaBetaGammaDelta-carry; trap on overflow
WAI LRRB 1 (AuxRegs[BetaR]+AlphaZ)^←[L+BetaL]
WB OB 1 ([S]+AlphaZ)^←[S-1]; S←S-2
WRI LRRB 1 ([L+BetaR]+AlphaZ)^←[L+BetaL]
WSB OB 1 ([S-1]+AlphaZ)^←[S]; S←S-2
Alpha is the first byte after the opcode. AlphaZ is Alpha zero-extended to 32 bits. AlphaS is Alpha sign-extended to 32 bits.
Beta is the second byte after the opcode. BetaZ is Beta zero-extended to 32 bits. BetaS is Beta sign-extended to 32 bits. When taken as a pair of four bit numbers, BetaL is the leftmost half of Beta, and BetaR is the rightmost half.
AlphaBeta is the unsigned unaligned halfword following the opcode byte, interpreted as Alpha*256 + Beta. AlphaBetaZ is AlphaBeta zero-extended to 32 bits. AlphaBetaS is AlphaBeta sign-extended to 32 bits.
AlphaBetaGammaDelta is the 32-bit unsigned unaligned quantity following the opcode byte. The number is interpreted as AlphaBeta*256*256 + Gamma*256 + Delta (where Gamma is the third byte after the opcode, Delta is the fourth byte after the opcode).
OI - Operation Implicit (the operand (if any) is implicit in the opcode).
OB - Operation Byte (the operand given by AlphaZ or AlphaS).
ODB - Operation Double Byte (the operand given by AlphaBetaZ or AlphaBetaS).
OQB - Operate Quad Byte (the operand given by AlphaBetaGammaDelta).
JBB - Jump Byte Byte (AlphaZ is the literal, PC+BetaS is the jump PC).
LR - Local Register (push or pop Locals[reg]).
LRB - Local Register Byte (push or pop (Locals[reg]+AlphaZ)^).
LRRB - Local Register Register Byte (BetaL denotes one of Locals, BetaR denotes one of Locals or AuxRegs, AlphaZ is an offset).
RR - Register to Register. Each operand (Ra, Rb, Rc) may be of the following:
Locals[n] one of the 16 local registers
AuxRegs[n] one of the 16 auxilliary registers
Constants[n] one of the 12 constant registers
[S], [S-1] the top of stack, or just below it
[S]-, [S-1]- stack operand with S decrement (Ra & Rb only)
[S+1]+ push onto the stack (for Rc only)
Locals and AuxRegs cannot be used in the same instruction.
QR - Quick Register. Rb is fully general, Ra and Rc are limited to:
0: Rc = [S], Ra = [S]
1: Rc = [S+1]+, Ra = [S]
2: Rc = [S+1]+, Ra = Constants[0]
3: Rc = [S+1]+, Ra = Constants[1]
RJB - Register Jump Byte. Rb is fully general, the jump PC is at PC+BetaS, Rs is limited to [S], [S]-, Constants[0] or Constants[1].
DRAGON Instruction Map
This instruction map shows the current placement of instruction codes in the opcode space. It has been arranged to minimize the decoding difficulty for the IFU. This map is subject to change.
Octal Form Len --0 --1 --2 --3 --4 --5 --6 --7
00- OI 1 xop xop xop xop xop xop xop xop
01- OI 1 xop xop xop xop xop xop xop xop
02- OI 1 LC0 LC1 LC2 LC3 LC4 LC5 LC6 LC7
03- OI 1 LC8 LC9 LC10 LC11 xop xop xop xop
04- OQB 5 xop xop xop xop xop xop xop xop
05- OQB 5 xop xop xop xop xop xop xop xop
06- OQB 5 xop DFC LIQB xop ADDQB SUBQB J5 JQB
07- OQB 5 xop xop xop xop xop xop xop xop
10- OI 1 OR AND RX BC ADD SUB LADD LSUB
11- OI 1 DUP DIS xop EXDIS SFC SFCI RETN JSD
12- OI 1 xop xop xop xop KFC xop J1 JSR
13- OI 1 xop xop xop xop xop xop xop xop
14- LR 1 LR0 LR1 LR2 LR3 LR4 LR5 LR6 LR7
15- LR 1 LR8 LR9 LR10 LR11 LR12 LR13 LR14 LR15
16- LR 1 SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7
17- LR 1 SR8 SR9 SR10 SR11 SR12 SR13 SR14 SR15
20- QR 2 QOR QAND QRX QBC QADD QSUB QLADD QLSUB
21- OB 2 ALS AL ASL AS CST xop RET xop
22- OB 2 LIP SIP LIB xop ADDB SUBB J2 JB
23- OB 2 RB WB RSB WSB xop xop xop PSB
24- LRB 2 LRI0 LRI1 LRI2 LRI3 LRI4 LRI5 LRI6 LRI7
25- LRB 2 LRI8 LRI9 LRI10 LRI11 LRI12 LRI13 LRI14 LRI15
26- LRB 2 SRI0 SRI1 SRI2 SRI3 SRI4 SRI5 SRI6 SRI7
27- LRB 2 SRI8 SRI9 SRI10 SRI11 SRI12 SRI13 SRI14 SRI15
30- RR 3 ROR RAND RRX RBC RADD RSUB RLADD RLSUB
31- RR 3 RXOR *** RFU *** RVADD RVSUB RUADD RUSUB
32- ODB 3 LGF LFC LIDB FSDB ADDDB SUBDB J3 JDB
33- +++ 3 RAI WAI RRI WRI IODA IOD ION ***
34- RJB 3 *** RJEB RJLB RJLEB *** RJNEB RJGEB RJGB
35- RJB 3 *** RJNEBJ RJGEBJ RJGBJ *** RJEBJ RJLBJ RJLEBJ
36- JBB 3 JEBB JNEBB JEBBJ JNEBBJ xop xop xop xop
37- ODB 3 SHL SHR SHDL SHDR xop xop xop xop
*** => Undefined behavior (reserved instruction)
+++ => Mixed format line (4 LRRB & 4 ODB)
xop => Takes Xop trap