The two technologies are additive layer (Augat) and subtractive layer (RayChem/ICL). The Augat technology has the largest design trules and will be considered worst case. All dimensions used in this paper are from Augat design rules unless otherwise stated.

The 4 chips in the processor assembly and the I/O chips can be connected as shown in Fig. 1. Also shown are the chip sizes, the expected power dissapation, the total pads and the signal pads used. All package assemblies will have the I/O interface driving the bus.

The width of the hybrid depends on the design rules of the interconect. The width of the hybrid for the processor for different technologies is shown in the Table below along with some electrical characteristics.

The proposed packaging approach (Fig. 2) based on Augat hybrid technology and design rules is to attach the six Dragon processor chips to a hybrid substrate measuring about 4 x 8 cm. Wire bonding would be used to connect the chip to hybrid interconnect. The hybrid substrate will be supported by a PCB assembly that extends about 1 mm beyond one long edge of the hybrid substrate. The suggested interconnect technology between the hybrid and the PCB support is similar to that used in leaded chip carriers. Small Z shaped metal tab arrays would be soldered to pads on the hybrid and the PCB. The suggested pitch is 635 microns (25 mils), commonly used in leaded single chip carriers.

Traces on the PCB would connect the high density hybrid interconnect pads to a set of through hole pads of pin-and-socket connectors. The connector pins would be placed on the standard 2.54 mm (0.1 inch) grid. The assembly would plug into mating connectors mounted on the main board. A 60 pin, two row connector, made by Fujitsu and Hypertronics looks promising. The overall dimensions are 80.8 x 6 mm. Three such connectors would allow 90 signal, 50 ground, 10 Vdd and 30 spare pins on the processor hybrid. Four connectors will fit on the 4 x 8 cm support PCB making 60 additional I/O pins available for use by display and memory controllers.

With the proposed connector arrangement, the signal line pitch would be about 1.27 mm (50 mils) using standard PCB density of two signal traces between through holes spaced at 2.54 mm centers. If the bus signal trace width is 0.2 mm (8 mils), the DC resistance of a 40 cm long fast bus trace would be about 0.7 ohm, assuming a copper trace thickness of 35 microns (1 ounce). The loss of received signal DC amplitude would be less than 2% for the worst case placement of source and destination. With the traces separated by about 1 mm, the maximum crosstalk between fast bus signals should be less than 2%.

A primary consideration for the layout of the hybrid is to minimize the length of the signal lines between the I/O chips and the fast bus. Both the capacitance and series resistance of these lines are critical. Capacitance loading at each tap on the 50 ohm fast bus line will produce cumulative reflections that degrade the signal/noise margin at the bus receivers. The tap capacitance with a good layout will probably be about 4 pf, measured at the edge of the hybrid. This assumes about 2.5 pf for the chip plus 1.5 pf for the interconnect. The PCB support and socket hardware will add about 5 pf. The assumptions are; main board through hole 1 pf, plug and socket 2 pf, support PCB through hole and interconnect trace 2 pf.

Preliminary simulations (of different geometry and loading) indicate, by rather questionable extrapolation, that bus waveform ripple of about 20% of the signal amplitude may occur with this large tap capacitance. The period of the ripple appears to be the round trip time between taps. The simulation indicates that the ripple decays by roughly 25% per cycle. This will extend the bus settling time by an amount determined by the noise immunity of the bus receiver. Things will improve when the the hybrid is connected directly to the main board. It may turn out that removing some of the main board ground plane for the 50 ohm bus near the taps can help reduce the apparent discontinuity.

Resistance in series with the driver will reduce the signal amplitude. The effect is twice as serious as that of resistance in the fast bus line on the main board because the DC load is 25 ohms at this point (two 50 ohm loads in parallel). Preliminary trial layouts indicate that the longest Pad Driver to bus interconnect path length may be about 10 mm. Raychem hybrid interconnect provides two signal layers of 5 micron aluminum with sheet resistance of about 0.006 ohms/square. The single layer line width required for a total resistance of 0.5 ohms would be 120 microns. In this part of the layout both levels can be used in parallel to cut the width in half. Augat hybrid interconnect provides two signal layers of 25 micron copper with sheet resistance of about 0.0005 ohms/square. However, the interconnect density is 2.5 times worse on the lower layer.

The main PCB can use either stripline (signal traces between ground planes) or microstrip construction (where the signal traces see a ground plane on only one side). An eight layer board is proposed which will allow stripline to be used for the fast bus and will prevent crosstalk into the bus from signals on the outside layers which can be used by the memory and display controllers.

The hybrid package heat dissipation path can use heat flow from the chips through the hybrid substrate to a copper sheet, perhaps about 1 mm thick, interposed between the support PCB and hybrid chip substrate. Thermal vias may be placed under the die attach sites, if necessary. The low thermal resistance path of the copper sheet will cary the thermal flow to the narrow edges with a temperature rise of about 10 degrees C. A thin copper cover may be attached to conduct the heat to the vertical air flow. The surface area of the cover is about 30 square cm. It will be increased by adding small fins.

We need time to make more careful exploration of at least the following points. The list is expected to grow.