* Single Ethernet Controller. Ethernet buffers might be constrained so that they do not cross page boundaries. Ethernet control blocks might reside at prescribed physical addresses.

* ROM for network ID.

* Floppy, 5.25 in.

* Hard disk, ST506/ST412.

* Possibly ESDI or SCSI.

* Disk buffers may be specified with virtual addresses (i.e. randomly crossing page boundaries).

* Keyboard and mouse, 9600 baud async.

* Medium speed (50Kbits) sync. or async. line, RS232C and optionally V35.

* 32 bits at 100 kHz.

To be determined.

* MP-LEDs.

* Boot buttons.

* Interrupt timers.

* Memory to memory data block mover.

* At least, provide something that can be converted into a commercial bus outside the Dragon-87 board. At best, implement a well supported commercial bus e.g. VME or Multibus.

* DMA devices are not expected to be supported by the commercial bus interface.

Should IO devices use virtual addresses? The disk should use virtual addresses; the commercial bus might also. It is considered desirable to avoid implementing a general IO mapping mechanism, if possible.

* Local microprocessor.

* ROM for Dragon-87 initial code (64-128 Kbytes) to support Disk/Ethernet booting.

* ROM for local microprocessor (possibly on-chip).

* Support for Dynabus and processor ID initialization.

The model for performing diagnostics is similar to that implemented by Midas for Dorados; the Dragon-87 is cycled by a test program running on an outboard D-machine connected via an RS232C line or some other convenient interface. More complex diagnostics will run directly on the Dragon-87. The complexity limit will be determined by the amount of local ROM available (4Kbytes?).

Will be either an AMD or Intel chip with appropriate glue. Should only consume the same area as the relevent section on the current Daybreak IOP board (2.25 x 4 in.) if the Intel chip is used. The Intel chip appears more suitable for testing purposes but suffers the disadvantage of holding onto the bus for long periods, typically 20 mS.

RS232C is a standard. The plan here is to use the SCC (Am 8530) and CIO (Z8036/8536). Between them these chips will support 56 Kbit and faster serial lines, provide a counter and drive MP-LED's. It would also handle keyboard and mouse. This chip combination requires some arcane software (Hal Murray has designated himself the expert on this subject).

NOTE: We are not interested in RS422 etc.

ST506 is probably the most ubiquitous for microcomputers and has the most product support. The drawbacks are limited speed (5 Mbits/sec) and limited disk size (less than 200 MBytes). Beyond these limits, ESDI and SCSI should seriously be considered. We are looking for a single chip disk controller. Examples: Am 9580, Signetics SCM 68454, National DP8466. The Am 9580 has the capability of scattered reads and writes in main memory which would avoid the problem of address translation.

NOTE: The current Daybreak uses a Signetics 8x305 microprocessor as the controller; the same chip used on some VME boards. This is an older technology which consumes more area than we can allow on Dragon-87. The cost reduced DayBreak will use an AMD 9580. Supporting floppies, ST506 and ESDI with a single chip appears possible. SCSI will require different peripherals. Both SCSI and ESDI would enable the use of tapes and optical disks.

This bus, although not a true system bus, is used to communicate with Xerox printers and various pieces of instrumentation in CSL and ICL. The question is, do we provide a dedicated connector or throw the controller board onto a standard system bus? Previous experience indicates that the TI 9914 is the right chip to use if we implement the interface ourselves.

The simplest expedient will be to provide this capability via a commercial bus.

RamDac by Brooktree. If this color display controller is used, the necessary control lines could be provided by the boot microprocessor in the I/O section.

The boot microprocessor will require some EEROM, UVROM, RAM and glue.

Clearly, some minimal intelligence is required to provide service task 2.1. The danger here, is the tendency to chose a processor that is too sophisticated such that one is immediately faced with the daunting task of developing massive piles of code for it (see Section 1) and chewing up real-estate with the other support chips usually required by 32 bit processors. The proposal is to choose a simpler processor, like a 6502, or its more recent CMOS successor, which can read the initialization code blown into a PROM. As well as keeping the chip count down, there may be some leverage provided by the fact that the Dorado base-board uses a 6502 and there are some in-house attendent code development tools.