Catalog Components
BigCache: [Indigo]<Dragon>Top>BigCache.df
Documentation: BCDesignDecisions.tioga
Cache2: [Indigo]<Dragon>Top>Cache2.df
CacheSims: [Indigo]<Dragon>Top>CacheSims.df
CommonMbus: [Indigo]<Dragon>Top>CommonMbus.df
Documentation: CommonMbusSpecs.tioga
CoreUtils: [Indigo]<Dragon>Top>CoreUtils.df
Commands: CoreUtils
CrossRAM4: [Indigo]<Dragon>Top>CrossRAM4.df
Documentation: CRCells.tioga
CRTest: [Indigo]<Dragon>Top>CRTest.df
Commands: CRTest
DBus: [Indigo]<Dragon>Top>DBus.df
Documentation: DBusDoc.tioga, DBusOldDoc.tioga
Keywords: DBus, LSSD, DynaBus, IOBridge, Bootstrap, Debug
Abstract: The DBus is used both to initialize a Dragon machine and to debug it. This document is intended to be used both as a convenient source for information about the DBus and as a reference manual for bus specifications.
Acknowledgements to Rick Barth, Jim Gasbarro, Ed McCreight and others who designed the first DBus and discussed on the new version.
DocCell4: [Indigo]<Dragon>Top>DocCell4.df
Documentation: [Indigo]<Dragon>Top>Documentation.df
Documentation: DragonDoc.form, DragonCatalog.tioga, DocumentNumbers.tioga, AUDoc.tioga, DisplayControllerStrawMan.tioga, DragonDiagnostics.tioga, DragonFP.tioga, DragonMesaChanges.tioga, DragonOpSum.tioga, DragonOverview.tioga, DragonPackaging.tioga, DragOps.tioga, EDMBusCompatibility.tioga, IFUDoc.tioga, InstrExec.tioga, MBusAnalysis.tioga, MemoryController.tioga, ModeMechanism.tioga, OpcodeChanges.tioga, RRChange.tioga, CacheSpecs.tioga, NewCacheNotes.tioga, ProcessorCacheSpecs.tioga, DesignRuleSummaryC.tioga, DragonCMOSDesignRulesC.tioga, HardwareNotes.tioga, IMSTesterNotes.tioga, WorkstationIOP.tioga, PackageNotes.tioga, PackagingSpecs.tioga, InstructionSet.tioga, InstructionSetSum.tioga, Memory.tioga, SingleProcOp.tioga, Timing.tioga, Traps.tioga, OnePageInstructionSetSummary.tioga
Dragoman: [Indigo]<Dragon>Top>Dragoman.df
Documentation: DragomanMemory.tioga, DragomanWaterlilyFile1.tioga, DragomanWaterlilyFile2.tioga, CacheStats.tioga
DragonCedarPlans: [Indigo]<Dragon>Top>DragonCedarPlans.df
Documentation: DragonBasement.tioga, DragonMesaChanges.tioga
DragonCMOSDesignRules: [Indigo]<Dragon>Top>DragonCMOSDesignRules.df
Documentation: DragonCMOSDesignRulesC.tioga, DesignRuleSummaryC.tioga, DragonCMOSDesignRulesD.tioga, DragonCMOSAdvisoryComments.tioga, DragonCMOSAdvisoryComments14Mar87.tioga, DragonCMOSToolingSpec.tioga, DragonCMOSToolingSpecB.tioga
DragonMemory: [Indigo]<Dragon>Top>DragonMemory.df
DynaBus: [Indigo]<Dragon>Top>DynaBus.df
Documentation: DynaBusLogicalSpecifications.tioga, DynaBusConsistencyAlgorithm.tioga, DynaBusGuidelines.tioga
ICTest: [Indigo]<Dragon>Top>ICTest.df
IFU2: [Indigo]<Dragon>Top>IFU2.df
Commands: IFU2
IFUCore: [Indigo]<Dragon>Top>IFUCore.df
Commands: IFUCore
IFUPack: [Indigo]<Dragon>Top>IFUPack.df
Documentation: IFUNotes.tioga
Commands: IFUPack, IFUBuild, IFUReBuild, IFUPlot
IFUPLA: [Indigo]<Dragon>Top>IFUPLA.df
Commands: IFUPLA
IFUTest: [Indigo]<Dragon>Top>IFUTest.df
Documentation: IFUCkList.tioga, IFUMintNotes.tioga
Commands: IFUBottom
June87: [Indigo]<Dragon>Top>June87.df
Documentation: June87.tioga
MapCache: [Indigo]<Dragon>Top>MapCache.df
Documentation: MapCacheLayout.tioga, MCKnownBugs.tioga, MCSil.dale
MapProcessor: [Indigo]<Dragon>Top>MapProcessor.df
Documentation: MapProcessorDoc.tioga, OldMapProcessorDoc.tioga
Keywords: Dragon, Multiprocessors, Address Mapping, Virtual Memory, Map Cache
Abstract: This document describes the Dragon Map Processor, the device that maps virtual addresses to real and provides per-page memory protection in Dragon. The Map Processor's main features are fast response to mapping requests; the use of a small, fixed fraction of main memory for mapping; the support of multiple address spaces with sharing; and an organization in which both function and performance can be enhanced relatively easily after initial implementation.
MBus: [Indigo]<Dragon>Top>MBus.df
Documentation: MBusSpecs.tioga
Memory: [Indigo]<Dragon>Top>Memory.df
MemoryController: [Indigo]<Dragon>Top>MemoryController.df
Documentation: MemoryControllerSpec.tioga
MemorySystem: [Indigo]<Dragon>Top>MemorySystem.df
Documentation: HCMSpecs.tioga, MSDesignDecisions.tioga
PBus: [Indigo]<Dragon>Top>PBus.df
Documentation: PBusSpecs.tioga
PLAOps: [Indigo]<Dragon>Top>PLAOps.df
Commands: PLAOps, PLAOpsCompress
REFBit: [Indigo]<Dragon>Top>REFBit.df
Created by: Don Curry
Maintained by: Don Curry <Curry.pa>
Documentation: REFBitDoc.tioga
Keywords: REF BitArray
Commands: REFBit, REFBitFormat
Abstract: When designing and simulating hardware, it's sometimes useful to deal with instances of arbitray Cedar TYPEs as if they were arrays of bits.
SmallCache: [Indigo]<Dragon>Top>SmallCache.df
Documentation: SCBmCode.tioga, SCDesignDecisions.tioga, SCDataPath.dale, SCTiming.dale, SCTiming.tioga, SCAlgorithm.tioga, SCPInterface.tioga, SCPInterface.dale, SCActionItems.tioga, SCStatus3Mar87.tioga, SCCtlSignals.tioga, SCDesignReview.dale, SCDesignReview.tioga, OldSCDesignDecisions.tioga, OldCacheSpecs.tioga, OldSCTiming.tioga
UncountedAssignHack: [Indigo]<Dragon>Top>UncountedAssignHack.df
Commands: UncountedAssignHack
WeitekIeee: [Indigo]<Dragon>Top>WeitekIeee.df