<> <> <> <> <<>> <> <<>> DIRECTORY Basics USING [DoubleShiftLeft], DragOpsCross USING [Word, ProcessorRegister, XopBase, TrapBase, TrapWidthBytes, bytesPerWord, TrapIndex, Inst, KernalLimit], --XopBase, TrapBase, TrapWidthBytes, Inst, wordsPerPage, bytesPerWord, charsPerWord, bitsPerByte, bitsPerCharacter, bitsPerWord, logWordsPerPage, logBitsPerByte, logBitsPerChar, logBytesPerWord, logCharsPerWord, logBitsPerWord, logBytesPerPage, PageCount, PageNumber, maxPagesInVM, SixBitIndex, FiveBitIndex, Word, TwoWords, FourBitIndex, Half, ThreeBitIndex, FourHalves, TwoHalves, Byte, ZerosByte, OnesByte, EightBytes, FourBytes, ByteIndex, BytesPerWord, TwoBytes, Comparison, ByteAddress, WordAddress, FieldDescriptor, TrapWidthWords, KernalLimit, TrapIndex, StackUnderflowTrap, IFUPageFaultTrap, ResetTrap, IFUStackOverflowTrap, EUStackOverflowTrap, RescheduleTrap, ALUCondOver, ALUCondBC, ALUCondIL, ALUCondDO, EUPageFault, EUWriteFault, AUFault, euStack, euJunk, euMAR, euField, euConstant, euAux, euBogus, euLast, ifuXBus, ifuStatus, ifuSLimit, ifuYoungestL, ifuYoungestPC, ifuEldestL, ifuEldestPC, ifuBogus, ifuL, ifuS, ifuPC, ifuLast, IFUStatusRec, IFUStackIndex, IFUStackSize, IFUOverflow, EUStackIndex, EUStackSize, EULocalIndex, EULocals, EUAuxIndex, EUAuxRegs, EUConstIndex, EUConstants, IOLocation, ioRescheduleRequest, ioResetRequest DragOpsCrossUtils USING [CardToWord, IntToWord, CardToByte], --BytePCToWordAddress, WordAddressToBytePC, IOOperandToCard, CardToIOOperand, FieldDescriptorToCard, CardToFieldDescriptor, StatusToWord, WordToStatus, BytesToWord, BytesToHalf, WordToBytes, HalfToBytes, HalvesToWord, WordToHalves, HighHalf, LowHalf, LeftHalf, RightHalf, SwapHalves, WordToInt, IntToWord, WordToCard, HalfToCard, ByteToCard, CardToWord, CardToHalf, CardToByte, DragAnd, DragOr, DragXor, DragNot, VanillaAdd, VanillaSub, AddDelta, HalfNot, HalfAnd, HalfOr, HalfXor, HalfShift, DoubleWordShiftLeft, SingleWordShiftLeft, SingleWordShiftRight, TrapIndexToBytePC, XopToBytePC HandCoding, --Has opcode and register defs. HandCodingPseudos, --GenLabel, GenLabelHere, SetLabel, Halt, Pause, MakeLabelGlobal, UseLabel8B, UseLabel16, UseLabel32, ProcedureEntry, ProcedureExit, EnableTraps, IndexedJump, SetupField, ExtractField, ShiftLeft, LoadProcessorReg, StoreProcessorReg, DisableTraps, CauseReschedule, CauseReset, GetSPLimit, SetSPLimit, GetL, SetL, GetYoungestPC, GetYoungestL, GetEldestPC, GetEldestL, SetYoungestPC, SetYoungestL, SetEldestPC, SetEldestL HandCodingSupport; --Area, GetCurrentArea, ReserveData, SetOutputPC, GetProc, PutProc, ProcList, NewArea, GenWithArea, Gen1WithArea, ForceOut, GetOutputPC, WordAlign, OutputByte, OutputOneByte, OutputAlphaBeta, OutputAlphaBetaGammaDelta, OutputWord GenTraps: CEDAR PROGRAM IMPORTS Basics, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport = BEGIN OPEN DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport; Word: TYPE = DragOpsCross.Word; ProcessorRegister: TYPE = DragOpsCross.ProcessorRegister; <> ifuSLimit: CARDINAL = LOOPHOLE[ProcessorRegister.ifuSLimit, CARDINAL]; <> ifuEldestPC: CARDINAL = LOOPHOLE[ProcessorRegister.ifuEldestPC, CARDINAL]; ifuEldestL: CARDINAL = LOOPHOLE[ProcessorRegister.ifuEldestL, CARDINAL]; ifuYoungestPC: CARDINAL = LOOPHOLE[ProcessorRegister.ifuYoungestPC, CARDINAL]; ifuYoungestL: CARDINAL = LOOPHOLE[ProcessorRegister.ifuYoungestL, CARDINAL]; ifuStatus: CARDINAL = LOOPHOLE[ProcessorRegister.ifuStatus, CARDINAL]; euMAR: CARDINAL = LOOPHOLE[ProcessorRegister.euMAR, CARDINAL]; KernelLimit: LONG CARDINAL = DragOpsCross.KernalLimit; <> aux0: AuxRegSpec = [aux[0]]; aux1: AuxRegSpec = [aux[1]]; aux2: AuxRegSpec = [aux[2]]; aux3: AuxRegSpec = [aux[3]]; aux4: AuxRegSpec = [aux[4]]; aux5: AuxRegSpec = [aux[5]]; aux6: AuxRegSpec = [aux[6]]; aux14: AuxRegSpec = [aux[14]]; aux15: AuxRegSpec = [aux[15]]; const5: ConstSpec = [const[5]]; const6: ConstSpec = [const[6]]; const7: ConstSpec = [const[7]]; const8: ConstSpec = [const[8]]; const9: ConstSpec = [const[9]]; const10: ConstSpec = [const[10]]; const11: ConstSpec = [const[11]]; <<>> All: PROC = { area: Area = GetCurrentArea[]; oldPC: LONG CARDINAL; start: Label = GenLabel[]; dummy: Label = GenLabel[]; initL: Label = GenLabel[]; <> IFUStackOverflow: Label = GenLabel[]; AddressCheck: Label = GenLabel[]; Overflow: Label = GenLabel[]; BoundsCheck: Label = GenLabel[]; LispNaN: Label = GenLabel[]; UserModeViolation: Label = GenLabel[]; EUPageFlt: Label = GenLabel[]; EUPageFaultBad: Label = GenLabel[]; EUWPFlt: Label = GenLabel[]; EUWPFaultBad: Label = GenLabel[]; IFUPageFault: Label = GenLabel[]; IFUPageFaultBad: Label = GenLabel[]; IFUPageFaultPC: LONG CARDINAL = 300000000B; EUPageFaultAddress: LONG CARDINAL = IFUPageFaultPC/4; EUStackOverflow: Label = GenLabel[]; EUStkOvfBad: Label = GenLabel[]; Reschedule: Label = GenLabel[]; RescheduleBad: Label = GenLabel[]; KFCTrap: Label = GenLabel[]; KFCBad: Label = GenLabel[]; Xop1Trap: Label = GenLabel[]; Xop1Bad: Label = GenLabel[]; Xop2Trap: Label = GenLabel[]; Xop2Bug: Label = GenLabel[]; Xop3Trap: Label = GenLabel[]; Xop3Bug: Label = GenLabel[]; Xop5Trap: Label = GenLabel[]; Xop5Bug: Label = GenLabel[]; enterIFUStatusTest: Label = GenLabel[]; enterIFUStackOverflowTest: Label = GenLabel[]; enterSLimitTest: Label = GenLabel[]; enterRescheduleTest: Label = GenLabel[]; enterIFUPageFaultTest: Label = GenLabel[]; enterEUPageFaultTest: Label = GenLabel[]; enterModeFaultPriorityTest: Label = GenLabel[]; enterAddressCheckPriorityTest: Label = GenLabel[]; <> <<>> <> <<>> <> <> FillXop: PROC [inst: CARDINAL, dest: Label] = { SetOutputPC[inst * DragOpsCross.TrapWidthBytes + DragOpsCross.XopBase * DragOpsCross.bytesPerWord]; drJDB[UseLabel16[dest]]; }; <> FillTrap: PROC [tx: DragOpsCross.TrapIndex, dest: Label] = { SetOutputPC[LOOPHOLE[tx, CARDINAL] * DragOpsCross.TrapWidthBytes + DragOpsCross.TrapBase * DragOpsCross.bytesPerWord]; drJDB[UseLabel16[dest]]; }; <<16 bytes between consecutive trap instructions is insufficient for StandardTrap, so the trap instruction must be filled separately with FillTrap[TrapName, dest]. aux8 has previously been loaded with a code for the trap presently expected (or 0 if none), and an opcode which is supposed to trap is followed by enough Pause[] opcodes to fill out 6 bytes (i.e., enough for a 5-byte trapping opcode and a 1-byte Pause[] after it); then if no trap occurs, the first Pause[] after the opcode will stop simulation; or if the wrong trap occurs, the mismatch on aux8 will cause Pause[] to occur. Otherwise, the trap procedure will return to the 6th byte after the location that trapped.>> StandardTrap: PROC [dest: Label, code: CARDINAL] = { TrapUnexpected: Label = GenLabel[]; SetLabel[dest]; drALS[0]; --ALS[1 - nargs], where nargs includes 1 for IFUstatus drLIB[code]; drRJNEB[popSrc, aux8, UseLabel8B[TrapUnexpected]]; <> GetYoungestPC[]; drRVADD[topDst, const4, topSrc]; SetYoungestPC[]; drRETK[377B]; --RETK[nResults - 1] SetLabel[TrapUnexpected]; Pause[]; }; <> WriteAtAddress: PROC [addr: LONG CARDINAL] ~ { <> oldPC: LONG CARDINAL = GetOutputPC[area]; bytePC: LONG CARDINAL _ Basics.DoubleShiftLeft[[lc[addr]], 2].lc; SetOutputPC[bytePC]; --pc is a byte address OutputWord[area, IntToWord[-1], FALSE]; SetOutputPC[oldPC]; drLC0[]; drLIQB[CardToWord[addr]]; drWB[0]; }; <> WriteTrapAtAddress: PROC [addr: LONG CARDINAL] ~ { WriteAtAddress[addr]; Pause[]; Pause[]; Pause[]; Pause[]; }; <> <<>> <> <<>> <> <<>> GenIFUStatus: PROC [] ~ { Bad0: Label = GenLabel[]; userOK0: Label = GenLabel[]; UCall1: Label = GenLabel[]; UCall2: Label = GenLabel[]; UJump1: Label = GenLabel[]; JQBNop0: Label = GenLabel[]; SetLabel[enterIFUStatusTest]; <> drLIQB[CardToWord[KernelLimit]]; drROR[aux0, topSrc, popSrc]; <> drLIB[20B + 10B + 2B]; --User mode + trapsEnabledKeep + rescheduleKeep drSIP[ifuStatus]; drLIP[ifuStatus]; <> drJEBBJ[20B+2B, UseLabel8B[userOK0]]; SetLabel[Bad0]; Pause[]; SetLabel[userOK0]; <> drROR[aux9, aux0, aux1]; drROR[aux9, aux2, aux3]; drROR[aux10, aux4, aux5]; drROR[aux11, aux6, aux7]; drROR[aux12, aux8, aux9]; drROR[aux13, aux10, aux11]; drROR[aux14, aux12, aux13]; drROR[aux15, aux14, aux14]; drROR[aux15, aux15, aux15]; drROR[pushDst, const0, const1]; --1st push drROR[topDst, const2, const3]; drROR[pushDst, const4, const5]; --2nd push drROR[belowDst, const6, const7]; drROR[topDst, const8, const9]; drROR[topDst, const10, const11]; drLIP[0]; --3rd push drLIP[127]; --4th push drLIP[159]; --5th push <> drLFC[3]; drLIP[ifuYoungestL]; --6th push drLIP[ifuYoungestPC]; --7th push drLIP[ifuEldestL]; --8th push drLIP[ifuSLimit]; --9th push drLIP[ifuStatus]; --10th push drASL[377B]; --0 pushes on the EU stack, 1 call on the IFU stack <= 100000000B) in user mode.>> WriteAtAddress[ KernelLimit]; WriteAtAddress[ 200000000B]; WriteAtAddress[ 400000000B]; WriteAtAddress[ 1000000000B]; WriteAtAddress[ 2000000000B]; WriteAtAddress[ 4000000000B]; <> --WriteAtAddress[10000000000B]; --WriteAtAddress[20000000000B]; <> drLIQB[CardToWord[KernelLimit]]; drIOS[2B]; drLIQB[CardToWord[ 200000000B]]; drIOS[2B]; drLIQB[CardToWord[ 400000000B]]; drIOS[2B]; drLIQB[CardToWord[ 1000000000B]]; drIOS[2B]; drLIQB[CardToWord[ 2000000000B]]; drIOS[2B]; drLIQB[CardToWord[ 4000000000B]]; drIOS[2B]; <> --drLIQB[CardToWord[10000000000B]]; drIOS[2B]; --drLIQB[CardToWord[20000000000B]]; drIOS[2B]; drAS[372B]; --0 pushes again <> drLC0[]; drDUP[]; drADD[]; --1st push = reg0 drLC1[]; --2 pushes drLIDB[0]; drLIQB[CardToWord[0]]; --4 pushes drLRn[reg11]; --5 pushes drQADD[topAtop, const0]; drRADD[belowDst, topSrc, belowSrcPop]; --4 pushes drSUB[]; --3 pushes drQSUB[topAtop, const0]; drRSUB[belowDst, popSrc, belowSrc]; --2 pushes drQLADD[topAtop, const0]; drRLADD[belowDst, popSrc, const0]; --1 push drQLSUB[topAtop, const0]; --1 push drRLSUB[pushDst, popSrc, const0]; drRUADD[belowDst, const0, popSrc]; --0 pushes drRUSUB[pushDst, const0, const0]; --1 push drRVADD[pushDst, const0, topSrc]; --2 pushes drRVSUB[topDst, topSrc, const0]; drAND[]; --1 push drQAND[pushAtop, const0]; --2 pushes drRAND[topDst, topSrc, topSrc]; drOR[]; --1 push drQOR[pushAtop, const0]; --2 pushes drADDB[0]; drSUBB[0]; drADDDB[0]; drSUBDB[0]; drRXOR[topDst, topSrc, topSrc]; drFSDB[444]; --1 push drRFU[pushDst, topSrc, topSrc]; --2 pushes drSHD[333]; --1 push drSHL[111]; --1 push drSHR[222]; --1 push drJ1[]; drJ2[]; Pause[]; drJ3[]; Pause[]; Pause[]; drJ5[]; Pause[]; Pause[]; Pause[]; Pause[]; drJDB[3]; drJQB[UseLabel32[JQBNop0]]; SetLabel[JQBNop0]; drEXDIS[]; --0 pushes drLIDB[0]; --1 push drASL[377B]; --0 pushes, 0 locals (S _ 0B, L = 1B) drAL[0]; drLIQB[CardToWord[KernelLimit]]; --legal address already used, 1 push FOR I: CARDINAL IN [0..17) DO drDUP[]; ENDLOOP; drSRn[reg0]; --Now have L = 1B, S = 21B (= 16 locals, 1 push) drLRIn[reg0, 0]; drSRIn[reg0, 0]; drDUP[]; drJEBB[0, 3]; drDUP[]; drJNEBB[0, 3]; drDUP[]; drJNEBBJ[0, 3]; drRJEB[topSrc, topSrc, 3]; drRJEBJ[topSrc, topSrc, 3]; drRJGB[topSrc, topSrc, 3]; drRJGBJ[topSrc, topSrc, 3]; drRJLB[topSrc, topSrc, 3]; drRJLBJ[topSrc, topSrc, 3]; drRJGEB[topSrc, topSrc, 3]; drRJGEBJ[topSrc, topSrc, 3]; drRJLEB[topSrc, topSrc, 3]; drRJLEBJ[topSrc, topSrc, 3]; drRJNEB[topSrc, topSrc, 3]; drRJNEBJ[topSrc, topSrc, 3]; --Still have 1 push (L = 1B, S = 21B) drLIQB[CardToWord[KernelLimit - 1]]; --2 pushes drRBC[topDst, topSrc, belowSrc]; --won't trap drQBC[topAtop, belowSrc]; --won't trap drDIS[]; drLIQB[CardToWord[KernelLimit + 1]]; drBC[]; --1 push drDUP[]; --2 pushes drLC0[]; drRX[]; drDIS[]; --1 push drQRX[pushAtop, const0]; drDIS[]; drLGF[0]; drDIS[]; --(aux0 was initialized to KernelLimit above) drRAI[reg1, aux0, 0]; drDUP[]; drRB[0]; drDIS[]; drRRI[reg1, reg13, 0]; --(reg0 .. reg15 were set to KernelLimit above) drRRX[reg1, reg13, const0]; drRSB[0]; drDIS[]; drWAI[reg1, aux0, 0]; drWRI[reg1, reg13, 0]; drLC0[]; drWSB[0]; --Still have 1 push drLIB[1]; drLC0[]; drCST[0]; drAS[374B]; --0 pushes drLIB[1]; drJS[]; drDFC[UseLabel32[UCall1]]; drLFC[UseLabel16[UCall2]]; drLIB[13]; drROR[aux8, topSrc, popSrc]; --Indicate XOP1 trap expected OutputByte[area, CardToByte[1B]]; drLIB[14]; drROR[aux8, topSrc, popSrc]; --Indicate XOP2 trap expected OutputAlphaBeta[area, (234B * 400B) + 123B]; drLIB[15]; drROR[aux8, topSrc, popSrc]; --Indicate XOP3 trap expected OutputByte[area, CardToByte[364B]]; OutputAlphaBeta[area, 234B]; drLIB[16]; drROR[aux8, topSrc, popSrc]; --Indicate XOP5 trap expected OutputByte[area, CardToByte[40B]]; OutputWord[area, CardToWord[345B]]; drLIB[12]; drROR[aux8, topSrc, popSrc]; --Indicate KFC trap expected drKFC[]; <> drROR[aux8, const0, const0]; --Indicate no traps expected drLIB[20B + 4B + 2B]; --User mode + trapsEnabled + rescheduleKeep drSIP[ifuStatus]; drLIQB[CardToWord[KernelLimit]]; --1 push drLIQB[UseLabel32[UCall1]]; --2 pushes drPSB[0]; --1 push drAS[1]; --2 pushes drSFC[]; --1 push drSFCI[]; drJB[UseLabel8A[UJump1]]; SetLabel[UCall1]; drRETN[]; SetLabel[UCall2]; drALS[377B]; --L _ S-1 drRET[1B]; --S _ L+1 SetLabel[UJump1]; drASL[17B]; --16 local registers, 0 EU pushes, 1 call on the IFU stack <> drLIB[8]; --1 push drROR[aux8, topSrc, topSrc]; --Indicate mode fault trap expected (aux8 = 8) <> drROR[aux0, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[aux1, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[aux2, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[aux3, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[aux4, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[aux5, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[aux6, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[aux7, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const0, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const1, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const2, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const3, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const4, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const5, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const6, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const7, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const8, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const9, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const10, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; drROR[const11, popSrc, topSrc]; Pause[]; Pause[]; Pause[]; <> <> drSIP[0]; Pause[]; Pause[]; Pause[]; Pause[]; drSIP[242]; Pause[]; Pause[]; Pause[]; Pause[]; drSIP[246]; Pause[]; Pause[]; Pause[]; Pause[]; <> drLIP[ifuEldestPC]; Pause[]; Pause[]; Pause[]; Pause[]; <> drLIB[20B + 10B + 2]; drLFC[4]; Pause[]; --RETK returned in user mode drRETK[377B]; Pause[]; Pause[]; Pause[]; Pause[]; drDIS[]; --16 locals, 1 push, 2 calls on the IFU stack < Kernel mode required 01x => address check x0 => read x1 => write Determine whether or not these operations get a ModeFault trap in user mode.>> drIOL[4B]; Pause[]; Pause[]; Pause[]; --[S+1] _ PRead[AlphaZ, BetaZ]; S _ S+1. drION[4B]; Pause[]; Pause[]; Pause[]; --[S+1] _ PRead[AlphaZ, BetaZ]. drIOS[4B]; Pause[]; Pause[]; Pause[]; --[S] _ PRead[AlphaZ + [S], BetaZ]. <> drIOL[177777B]; Pause[]; Pause[]; Pause[]; --PWrite[AlphaZ, BetaZ, [S]]; S _ S-1. drION[177777B]; Pause[]; Pause[]; Pause[]; --PWrite[AlphaZ, BetaZ, [S]]. drIOS[177777B]; Pause[]; Pause[]; Pause[]; --PWrite[AlphaZ + [S], BetaZ, [S-1]]; S _ S-2. drLIB[4]; drROR[aux8, popSrc, topSrc]; --Indicate Address Check trap expected <> drIOL[2B]; Pause[]; Pause[]; Pause[]; --[S+1] _ PRead[AlphaZ, BetaZ]; S _ S+1. drION[2B]; Pause[]; Pause[]; Pause[]; --[S+1] _ PRead[AlphaZ, BetaZ]. drLC0[]; drIOS[2B]; Pause[]; Pause[]; Pause[]; --[S] _ PRead[AlphaZ + [S], BetaZ]. drLIB[377B]; drIOS[2B]; Pause[]; Pause[]; Pause[]; drLIDB[177400B]; drIOS[2B]; Pause[]; Pause[]; Pause[]; drLIQB[CardToWord[400000B]]; drIOS[2B]; Pause[]; Pause[]; Pause[]; drLIQB[CardToWord[7000000B]]; drIOS[2B]; Pause[]; Pause[]; Pause[]; drLIQB[CardToWord[70000000B]]; drIOS[2B]; Pause[]; Pause[]; Pause[]; drLIQB[CardToWord[37777777B]]; drIOS[2B]; Pause[]; Pause[]; Pause[]; drASL[17B]; --16 locals, 0 pushes, 2 calls on IFU stack <> WriteTrapAtAddress[ 377B]; WriteTrapAtAddress[ 400B]; WriteTrapAtAddress[ 7000B]; WriteTrapAtAddress[ 70000B]; WriteTrapAtAddress[ 700000B]; WriteTrapAtAddress[ 3000000B]; <<4000000B will conflict with program>> WriteTrapAtAddress[ 5000000B]; WriteTrapAtAddress[70000000B]; WriteTrapAtAddress[77777777B]; <> drASL[17B]; --16 locals, 0 pushes on the EU stack, 2 calls on the IFU stack, user mode drLIB[12]; drROR[aux8, popSrc, topSrc]; --Indicate KFC trap expected drKFC[]; <> drROR[aux8, const0, const0]; --Indicate no traps expected FOR I: CARDINAL IN [0..1] DO GetEldestPC[]; ENDLOOP; }; <> GenIFUStackOverflow: PROC [] ~ { UCall3: Label = GenLabel[]; JQBNop1: Label = GenLabel[]; exitIFUStackOverflowTest: Label = GenLabel[]; eleventhCall: Label = GenLabel[]; drJB[UseLabel8A[enterIFUStackOverflowTest]]; SetLabel[UCall3]; Pause[]; --DFC, SFC, or SFCI trap was expected but didn't. SetLabel[enterIFUStackOverflowTest]; drASL[377B]; --0 locals, 0 pushes on the EU stack, 0 calls on the IFU stack drLIB[40B + 4B + 2B]; drSIP[ifuStatus]; --UserModeKeep + TrapsEnabled + RescheduleKeep <> drLFC[3]; --1 calls drLFC[3]; --2 calls drLFC[3]; --3 calls drLFC[3]; --4 calls drLFC[3]; --5 calls drLFC[3]; --6 calls drLFC[3]; --7 calls drLFC[3]; --8 calls drLFC[3]; --9 calls drLFC[3]; --10 calls drLFC[UseLabel16[eleventhCall]]; --11 calls <> drJDB[UseLabel16[exitIFUStackOverflowTest]]; --10 calls SetLabel[eleventhCall]; <> drLIB[40B + 4B + 2B]; drSIP[ifuStatus]; --UserModeKeep + TrapsEnabled + RescheduleKeep <> drJ1[]; drJ2[]; Pause[]; drJ3[]; Pause[]; Pause[]; drJ5[]; Pause[]; Pause[]; Pause[]; Pause[]; drJB[2]; drJDB[3]; drJQB[UseLabel32[JQBNop1]]; SetLabel[JQBNop1]; drLIB[1]; drJS[]; <> drLIB[2]; drLIB[1]; drQBC[pushAtop, belowSrc]; drDIS[]; drRBC[pushDst, reg1, reg0]; drDIS[]; drEXDIS[]; drLIB[2]; drBC[]; drLIB[1]; drROR[aux8, popSrc, topSrc]; --Indicate IFU stack overflow expected <> drLFC[3]; Pause[]; Pause[]; Pause[]; drDFC[UseLabel32[UCall3]]; Pause[]; drLIQB[UseLabel32[UCall3]]; drSFC[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; <<1, 2, 3, and 5-byte Xops should cause IFU stack overflow trap>> OutputByte[area, CardToByte[1B]]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; OutputAlphaBeta[area, (234B * 400B) + 123B]; Pause[]; Pause[]; Pause[]; Pause[]; OutputByte[area, CardToByte[364B]]; OutputAlphaBeta[area, 234B]; Pause[]; Pause[]; Pause[]; OutputByte[area, CardToByte[40B]]; OutputWord[area, CardToWord[345B]]; Pause[]; drKFC[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; <> drLIB[1]; drLIB[2]; drQBC[pushAtop, belowSrc]; Pause[]; Pause[]; Pause[]; Pause[]; drRBC[pushDst, topSrc, belowSrc]; Pause[]; Pause[]; Pause[]; drEXDIS[]; drLIB[1]; drBC[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; <> drLIQB[CardToWord[10000000000B]]; drDUP[]; drLADD[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; <> drADD[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; <> drLIQB[CardToWord[EUPageFaultAddress]]; drRB[0]; Pause[]; Pause[]; Pause[]; Pause[]; <> drASL[17B]; --L = 1, S = 20B drLIB[21B]; drSIP[ifuSLimit]; drDUP[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; drDIS[]; drLIB[160B]; drSIP[ifuSLimit]; <> drLIB[20B + 4B + 2B]; drSIP[ifuStatus]; --User + TrapEnable + RescheduleKeep drRADD[const1, const0, const0]; Pause[]; Pause[]; Pause[]; <> drLC0[]; drWB[0]; Pause[]; Pause[]; Pause[]; Pause[]; drROR[aux8, const0, const0]; --Indicate no traps expected drRET[377B]; --returns from 11th call and trims stack SetLabel[exitIFUStackOverflowTest]; drLIB[12]; drROR[aux8, popSrc, topSrc]; --Indicate KFC trap expected drKFC[]; <> FOR I: CARDINAL IN [0..9] DO GetEldestPC[]; ENDLOOP; drASL[17B]; --L = 1, S = 20B, traps enabled, Kernel mode, 0 calls on the stack }; GenSLimit: PROC [] ~ { <> SLimitTest: PROC [SL: CARDINAL] ~ { drLIB[SL]; drSIP[ifuSLimit]; drROR[aux8, const1, const1]; drASL[SL]; Pause[]; Pause[]; Pause[]; Pause[]; --SLimit drASL[SL + 15]; Pause[]; Pause[]; Pause[]; Pause[]; --SLimit + 15 drROR[aux8, const0, const0]; drASL[SL + 16]; --SLimit + 16 drASL[SL - 1]; --SLimit - 1 drASL[0]; --SLimit }; ReschedRet: Label = GenLabel[]; <> SetLabel[enterSLimitTest]; drASL[7B]; --L = 1, S = 10B, traps enabled, Kernel mode, 0 calls on the stack drLIB[4B + 2B]; drSIP[ifuStatus]; --TrapsEnabled + RescheduleKeep drLIB[13B]; drSIP[ifuSLimit]; drLIB[9]; drROR[const1, popSrc, topSrc]; --const1 _ EU stk ovf code drROR[aux8, const1, const1]; --Indicate EU stack overflow trap expected drLIQB[CardToWord[KernelLimit]]; drSRn[reg0]; --Memory address for LRIn below drLC0[]; --S = 11B drDUP[]; --S = 12B <> drLFC[4]; Pause[]; <> drDUP[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; drLRn[reg2]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; drQADD[pushA0, const0]; Pause[]; Pause[]; Pause[]; Pause[]; drRADD[pushDst, const0, const0]; Pause[]; Pause[]; Pause[]; drLRIn[reg0, 0]; Pause[]; Pause[]; Pause[]; Pause[]; <= 40B in this test, so I changed the code to have fewer locals.>> FOR I: CARDINAL IN [1..16] DO drAS[I]; Pause[]; Pause[]; Pause[]; Pause[]; drASL[11B + I]; Pause[]; Pause[]; Pause[]; Pause[]; drRET[11B + I]; Pause[]; Pause[]; Pause[]; Pause[]; ENDLOOP; drASL[377B]; --S = 0, L = 1 (won't trap) drLIB[160B]; drSIP[ifuSLimit]; --S in [160B..177B] will trap drLIP[ifuEldestPC]; drDIS[]; --clear the call stack <> --drSRn[reg15]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; --drQAND[topAtop, popSrc]; Pause[]; Pause[]; Pause[]; Pause[]; --drRAND[belowDst, topSrc, popSrc]; Pause[]; Pause[]; Pause[]; --drSRIn[reg0, 0]; Pause[]; Pause[]; Pause[]; Pause[]; --drDIS[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; <> drROR[aux8, const0, const0]; --Indicate no trap expected drAL[377B]; --L _ 0 <> SLimitTest[4B]; SLimitTest[10B]; <<**Lizard won't allow the 20B, 40B, 100B, or 157B tests (out of envelope if alpha >= 40B)>> --SLimitTest[20B]; SLimitTest[1B]; drASL[377B]; --SLimitTest[40B]; --SLimitTest[100B]; SLimitTest[2B]; --SLimitTest[157B]; <> drLIB[21B]; drSIP[ifuSLimit]; drAL[1B]; --L = 1 again drASL[15B]; --S = 16B drLIB[6]; drROR[aux8, topSrc, popSrc]; --Bounds check should prevail drLIB[1]; drLIB[2]; --S = 20B (1 less than SLimit) drQBC[pushAtop, belowSrc]; Pause[]; Pause[]; Pause[]; Pause[]; drRBC[pushDst, topSrc, belowSrc]; Pause[]; Pause[]; Pause[]; <> drAS[376B]; drLIB[7]; drROR[aux8, topSrc, popSrc]; --NaN prevails drLIQB[CardToWord[10000000000B]]; drDUP[]; drLADD[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; drDIS[]; drLIB[5]; drROR[aux8, topSrc, popSrc]; --Overflow prevails drDUP[]; drADD[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; drDIS[]; drLIB[2]; drROR[aux8, topSrc, popSrc]; --EU page fault prevails drLIQB[CardToWord[EUPageFaultAddress]]; drRB[0]; Pause[]; Pause[]; Pause[]; Pause[]; drDIS[]; drLIB[2B]; drSIP[ifuStatus]; --RescheduleKeep (= disable traps) drLIQB[UseLabel32[ReschedRet]]; --Label for reschedule trap return drLIB[11]; drROR[aux8, topSrc, popSrc]; --Reschedule should prevail drLIB[4B + 1B]; --S = SLimit now drSIP[ifuStatus]; --TrapEnable + Reschedule <> Pause[]; <> SetLabel[ReschedRet]; drDIS[]; drLIB[20B + 4B + 2B]; drSIP[ifuStatus]; --User + TrapEnable + RescheduleKeep drLIB[8]; drROR[aux8, topSrc, topSrc]; --Mode fault prevails drRADD[const1, const0, const0]; Pause[]; Pause[]; Pause[]; drDIS[]; drLIB[4]; drROR[aux8, topSrc, popSrc]; --Address check prevails drLC0[]; drWB[0]; Pause[]; Pause[]; Pause[]; Pause[]; drDIS[]; drLIB[12]; drROR[aux8, topSrc, topSrc]; --KFC should prevail drKFC[]; <> drROR[aux8, const0, const0]; --No trap expected drLIB[160B]; drSIP[ifuSLimit]; drASL[17B]; --L = 1, S = 20B, traps enabled, Kernel mode, 0 calls on the stack }; <> GenReschedule: PROC [] ~ { RescheduleOK: Label = GenLabel[]; SetLabel[enterRescheduleTest]; drASL[17B]; --L = 1, S = 20B, 0 calls on the stack drLIQB[UseLabel32[RescheduleOK]]; --Reschedule trap will send control here drLIB[11]; drROR[aux8, popSrc, topSrc]; --Reschedule trap expected <> drLIB[40B + 4B + 1B]; --User mode keep + TrapEnable + Reschedule drSIP[ifuStatus]; Pause[]; <> SetLabel[RescheduleOK]; drROR[aux8, const0, const0]; --No traps expected drLIB[40B + 1B]; --User mode keep + Reschedule (= traps disabled) drSIP[ifuStatus]; --Shouldn't trap <> drLIB[40B + 4B]; drSIP[ifuStatus]; <> --CauseReschedule[]; <> --drJ1[]; drJ1[]; drJ1[]; drJ1[]; drJ1[]; --Pause[]; }; <> GenIFUPageFault: PROC [] ~ { oldPC: LONG CARDINAL; LFCFaultOK: Label = GenLabel[]; RETNFaultOK: Label = GenLabel[]; CJumpFOK0: Label = GenLabel[]; CJumpFOK1: Label = GenLabel[]; FallThruOK: Label = GenLabel[]; endIFUPFTest: Label = GenLabel[]; nearFaultPagePC0: LONG CARDINAL = 277777600B; nearFaultPagePC1: LONG CARDINAL = 310007600B; IFUPageFaultPC1: LONG CARDINAL = 310010000B; nearFaultPagePC2: LONG CARDINAL = 320007775B; --Must be page boundary - 3 SetLabel[enterIFUPageFaultTest]; drASL[377B]; --L = 1, S = 0 drLIB[4B + 2B]; drSIP[ifuStatus]; --TrapsEnabled + RescheduleKeep drLIQB[CardToWord[nearFaultPagePC0]]; --location to which page fault trap returns drLIB[10]; drROR[aux8, popSrc, topSrc]; --IFU page fault expected drJQB[CardToWord[IFUPageFaultPC]]; --Will cause IFU page fault oldPC _ GetOutputPC[area]; SetOutputPC[nearFaultPagePC0]; drLIQB[UseLabel32[LFCFaultOK]]; drLFC[IFUPageFaultPC - GetOutputPC[area]]; --IFU page fault next SetLabel[LFCFaultOK]; drLIQB[CardToWord[IFUPageFaultPC]]; SetYoungestPC[]; drLIQB[UseLabel32[RETNFaultOK]]; drRETN[]; --Will cause IFU page fault SetLabel[RETNFaultOK]; drLIQB[UseLabel32[CJumpFOK0]]; drRJEB[const0, const0, IFUPageFaultPC - GetOutputPC[area]]; --IFU page fault next SetLabel[CJumpFOK0]; drLIQB[UseLabel32[CJumpFOK1]]; drRJEBJ[const0, const0, IFUPageFaultPC - GetOutputPC[area]]; --IFU page fault next SetLabel[CJumpFOK1]; drLIQB[UseLabel32[FallThruOK]]; drJB[IFUPageFaultPC - GetOutputPC[area] - 1]; SetOutputPC[IFUPageFaultPC - 1]; drJ1[]; --Next instruction causes IFU page fault SetOutputPC[nearFaultPagePC1]; SetLabel[FallThruOK]; <> drROR[aux8, const0, const0]; --Indicate no traps expected <> drRJNEB[const0, const0, IFUPageFaultPC1 - GetOutputPC[area]]; <> drRJNEBJ[const0, const0, IFUPageFaultPC1 - GetOutputPC[area]]; drJB[IFUPageFaultPC1 - GetOutputPC[area] - 3]; SetOutputPC[IFUPageFaultPC1 - 3]; <> drRJEB[const0, const0, 370B]; SetOutputPC[IFUPageFaultPC1 - 3 - 10B]; drJQB[CardToWord[nearFaultPagePC2]]; SetOutputPC[nearFaultPagePC2]; <> drRJEBJ[const0, const0, 370B]; SetOutputPC[nearFaultPagePC2 - 10B]; drJQB[CardToWord[oldPC]]; SetOutputPC[oldPC]; <<**Should test EU stack overflow coincident with IFU page fault.>> }; <> GenEUPageFault: PROC [] ~ { OKState: Label = GenLabel[]; BadState: Label = GenLabel[]; SetLabel[enterEUPageFaultTest]; drASL[377B]; --L = 1, S = 0 drLIB[4B + 2B]; drSIP[ifuStatus]; --TrapsEnabled + RescheduleKeep drLIQB[CardToWord[EUPageFaultAddress]]; drROR[aux9, topSrc, topSrc]; drLIB[2]; drROR[aux8, popSrc, topSrc]; --EU page fault expected drRB[0]; Pause[]; Pause[]; Pause[]; Pause[]; drRJEBJ[topSrc, aux9, UseLabel8B[OKState]]; SetLabel[BadState]; Pause[]; SetLabel[OKState]; drLIB[123B]; drROR[aux10, popSrc, topSrc]; <> drRRX[aux10, popSrc, const0]; Pause[]; Pause[]; Pause[]; <> drLIB[123B]; drRJNEB[popSrc, aux10, UseLabel8B[BadState]]; <> drRJNEB[topSrc, aux9, UseLabel8B[BadState]]; drLIDB[123456B]; drWSB[0]; Pause[]; Pause[]; Pause[]; Pause[]; drLIDB[123456B]; drRJNEB[popSrc, belowSrcPop, UseLabel8B[BadState]]; drRJNEB[topSrc, aux9, UseLabel8B[BadState]]; drLIDB[111111B]; --new value drLIDB[122222B]; --old value drCST[0]; Pause[]; Pause[]; Pause[]; Pause[]; <> drLIDB[122222B]; drRJNEB[popSrc, belowSrcPop, UseLabel8B[BadState]]; drDIS[]; drSFCI[]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; drRJNEB[topSrc, aux9, UseLabel8B[BadState]]; <> <<[S] _ PRead[AlphaZ + [S], BetaZ] with address check.>> --drIOS[2B]; -- Pause[]; Pause[]; Pause[]; --drRJNEB[popSrc, aux9, UseLabel8B[BadState]]; --drLIB[123B]; --drROR[pushDst, aux9, const0]; <> --drIOS[3B]; --drRJNEB[popSrc, aux9, UseLabel8B[BadState]]; --drJNEBB[123B, UseLabel8B[BadState]]; }; <> GenModeFaultPriority: PROC [] ~ { SetLabel[enterModeFaultPriorityTest]; drASL[377B]; --L = 1, S = 0 drLIB[8]; drROR[aux8, topSrc, popSrc]; --code for ModeFault trap drLIB[20B + 4B + 2B]; drSIP[ifuStatus]; --User mode + TrapsEnabled + RescheduleKeep drLIQB[CardToWord[10000000000B]]; drDUP[]; <> drRLADD[const2, belowSrc, topSrc]; Pause[]; Pause[]; Pause[]; <> drRADD[const2, belowSrc, topSrc]; Pause[]; Pause[]; Pause[]; <> drRBC[const2, belowSrc, popSrc]; Pause[]; Pause[]; Pause[]; drDIS[]; drLC0[]; drLIQB[CardToWord[EUPageFaultAddress]]; <> drRRX[const2, popSrc, belowSrcPop]; Pause[]; Pause[]; Pause[]; <> drLC0[]; drIOS[7B]; Pause[]; Pause[]; Pause[]; drLIB[12]; drROR[aux8, topSrc, popSrc]; --Indicate KFC trap expected drKFC[]; <> drROR[aux8, const0, const0]; --No traps expected }; <> GenAddressCheckPriority: PROC [] ~ { SetLabel[enterAddressCheckPriorityTest]; drASL[377B]; --L = 1, S = 0 drLIB[20B + 4B + 2B]; drSIP[ifuStatus]; --UserMode + TrapsEnabled + RescheduleKeep drLIB[4]; drROR[aux8, topSrc, popSrc]; --Indicate address check expected drLC0[]; drLIQB[CardToWord[EUPageFaultAddress]]; drWB[0]; Pause[]; Pause[]; Pause[]; Pause[]; drLIB[12]; drROR[aux8, topSrc, popSrc]; --Indicate KFC trap expected drKFC[]; drROR[aux8, const0, const0]; --Indicate no traps expected }; SetLabel[dummy]; Pause[]; Pause[]; Pause[]; Pause[]; Pause[]; Halt[123B]; <<>> StandardTrap[IFUStackOverflow, 1]; --priority 2 <> <> StandardTrap[AddressCheck, 4]; StandardTrap[Overflow, 5]; StandardTrap[BoundsCheck, 6]; StandardTrap[LispNaN, 7]; StandardTrap[UserModeViolation, 8]; <> <> <> <> <<1-byte Xop (opcode = 1B) has code 13>> <<2-byte Xop (opcode 234B, alpha = 123B) has code 14>> <<3-byte Xop (opcode 364B, alphabeta = 234B) has code 15>> <<5-byte Xop (opcode 40B, alphabetagammadelta = 345B) has code 16>> SetLabel[EUPageFlt]; drALS[0]; --1 - nargs; nargs = 1 for ifuStatus drLIB[2]; drRJNEB[popSrc, aux8, UseLabel8B[EUPageFaultBad]]; <> drLIQB[CardToWord[EUPageFaultAddress]]; drLIP[euMAR]; drRJNEB[popSrc, belowSrcPop, UseLabel8B[EUPageFaultBad]]; GetYoungestPC[]; drRVADD[topDst, topSrc, const4]; SetYoungestPC[]; drRETK[377B]; --nResults -1; nResults = 0 SetLabel[EUPageFaultBad]; Pause[]; SetLabel[EUWPFlt]; drALS[0]; --1 - nargs; nargs = 1 for ifuStatus drLIB[3]; drRJNEB[popSrc, aux8, UseLabel8B[EUWPFaultBad]]; <> drLIQB[CardToWord[EUPageFaultAddress]]; drLIP[euMAR]; drRJNEB[popSrc, belowSrcPop, UseLabel8B[EUWPFaultBad]]; GetYoungestPC[]; drRVADD[topDst, topSrc, const4]; SetYoungestPC[]; drRETK[377B]; --nResults -1; nResults = 0 SetLabel[EUWPFaultBad]; Pause[]; SetLabel[EUStackOverflow]; drALS[0]; --1 - nargs; nargs = 1 for ifuStatus drLIB[9]; drRJNEB[popSrc, aux8, UseLabel8B[EUStkOvfBad]]; GetYoungestPC[]; drRVADD[topDst, topSrc, const4]; SetYoungestPC[]; drRETK[377B]; --nResults -1; nResults = 0 SetLabel[EUStkOvfBad]; Pause[]; SetLabel[IFUPageFault]; drALS[377B]; --1 - nargs; nargs = 2 (return PC and ifuStatus) drLIB[10]; drRJNEB[popSrc, aux8, UseLabel8B[IFUPageFaultBad]]; GetYoungestPC[]; <> drLIQB[CardToWord[IFUPageFaultPC]]; drRJNEB[popSrc, belowSrcPop, UseLabel8B[IFUPageFaultBad]]; drLRn[reg0]; SetYoungestPC[]; drEXDIS[]; drRETK[377B]; --nResults -1; nResults = 0 SetLabel[IFUPageFaultBad]; Pause[]; SetLabel[Reschedule]; drALS[377B]; --1 - nargs; nargs = 2 (return PC and ifuStatus) drLIB[11]; drRJNEB[popSrc, aux8, UseLabel8B[RescheduleBad]]; drLIB[74B]; drAND[]; --Clear RescheduleKeep and Reschedule in saved ifuStatus drLRn[reg0]; SetYoungestPC[]; drEXDIS[]; drRETK[377B]; --nResults -1; nResults = 0 SetLabel[RescheduleBad]; Pause[]; <> SetLabel[KFCTrap]; drLIB[12]; drRJNEB[popSrc, aux8, UseLabel8B[KFCBad]]; drDIS[]; --Discard the IFU status drLIP[ifuStatus]; <> drJNEBB[2B, UseLabel8B[KFCBad]]; drRETN[]; --Return to caller remaining in Kernel mode with traps disabled. SetLabel[KFCBad]; Pause[]; SetLabel[Xop1Trap]; drLIB[13]; drRJNEB[popSrc, aux8, UseLabel8B[Xop1Bad]]; drRETN[]; --Return to caller remaining in Kernel mode. SetLabel[Xop1Bad]; Pause[]; SetLabel[Xop2Trap]; drLIB[14]; drRJNEB[popSrc, aux8, UseLabel8B[Xop2Bug]]; drJNEBB[123B, UseLabel8B[Xop2Bug]]; --Discard the pushed Alpha drRETN[]; --Return to caller remaining in Kernel mode. SetLabel[Xop2Bug]; Pause[]; SetLabel[Xop3Trap]; drLIB[15]; drRJNEB[popSrc, aux8, UseLabel8B[Xop3Bug]]; drJNEBB[234B, UseLabel8B[Xop3Bug]]; --Discard the pushed AlphaBeta drRETN[]; --Return to caller remaining in Kernel mode. SetLabel[Xop3Bug]; Pause[]; SetLabel[Xop5Trap]; drLIB[16]; drRJNEB[popSrc, aux8, UseLabel8B[Xop5Bug]]; drJNEBB[345B, UseLabel8B[Xop5Bug]]; --Discard the pushed AlphaBetaGammaDelta drRETN[]; --Return to caller remaining in Kernel mode. SetLabel[Xop5Bug]; Pause[]; <> oldPC _ GetOutputPC[area]; FillXop[0, dummy]; --opcode 0 = Pause[] FillXop[377B, dummy]; --opcode 377B = Halt[xxx] FillXop[LOOPHOLE[DragOpsCross.Inst.dKFC, CARDINAL], KFCTrap]; FillXop[1B, Xop1Trap]; FillXop[234B, Xop2Trap]; FillXop[364B, Xop3Trap]; FillXop[40B, Xop5Trap]; FillTrap[ResetTrap, start]; FillTrap[IFUStackOverflowTrap, IFUStackOverflow]; FillTrap[EUPageFault, EUPageFlt]; FillTrap[EUWriteFault, EUWPFlt]; FillTrap[AddressCheckFault, AddressCheck]; FillTrap[ALUCondOver, Overflow]; FillTrap[ALUCondBC, BoundsCheck]; FillTrap[ALUCondIL, LispNaN]; FillTrap[ModeFault, UserModeViolation]; FillTrap[EUStackOverflowTrap, EUStackOverflow]; FillTrap[IFUPageFaultTrap, IFUPageFault]; FillTrap[RescheduleTrap, Reschedule]; SetOutputPC[oldPC]; ProcedureEntry[initL, 0]; drLIB[1]; SetYoungestL[]; -- L _ 1 on return <> drLIB[128-16-1]; SetSPLimit[]; ProcedureExit[0]; WordAlign[area]; <> SetLabel[start]; drLFC[UseLabel16[initL]]; --Initialize L to 1 drASL[255]; --and S = 0. drROR[aux8, const0, const0]; --Initialize aux8 to 0, meaning no traps expected. drLIB[6]; drROR[const4, popSrc, topSrc]; --Initialize const4 to 6 for the trap routines. <> drLIB[1]; drROR[const1, topSrc, topSrc]; drROR[const2, topSrc, topSrc]; drROR[const3, topSrc, topSrc]; drROR[const5, topSrc, topSrc]; drROR[const6, topSrc, topSrc]; drROR[const7, topSrc, topSrc]; drROR[const8, topSrc, topSrc]; drROR[const9, topSrc, topSrc]; drROR[const10, topSrc, topSrc]; drROR[const11, topSrc, topSrc]; drROR[aux1, topSrc, topSrc]; drROR[aux2, topSrc, topSrc]; drROR[aux3, topSrc, topSrc]; drROR[aux4, topSrc, topSrc]; drROR[aux5, topSrc, topSrc]; drROR[aux6, topSrc, topSrc]; drROR[aux7, topSrc, topSrc]; <> drLC0[]; drSIP[0]; drLC0[]; drSIP[127]; drLC0[]; drSIP[159]; <> FOR I: CARDINAL IN [0..15) DO drLC0[]; ENDLOOP; GenIFUStatus[]; GenIFUStackOverflow[]; GenSLimit[]; GenReschedule[]; GenIFUPageFault[]; GenEUPageFault[]; GenModeFaultPriority[]; GenAddressCheckPriority[]; Halt[177777B]; --Terminate here at the end of the program }; END.