Copyright © 1986, 1987 by Xerox Corporation. All rights reserved.

Edward Fiala March 5, 1986 10:49:41 am PST

McCreight February 16, 1987 10:56:29 am PST

Curry, September 11, 1986 2:40:33 pm PDT

Fiala November 7, 1986 6:44:21 pm PST Massive edits to fix program for the fact that Reschedule and address check are no longer implemented, for the fact that ifuStatus is no longer pushed on the EU stack on a trap, for the different way of enabling and disabling traps and entering user mode, for features which can now be tested with ← LizardLiverImpl.careful ← FALSE, and for the deimplementation of partial simulation for IOD, IODA, and ION.

Fiala April 3, 1987 4:21:46 pm PST Eliminate Reset, Halt, and Pause stuff
to run with GenDebugger. Add XPause[] error halt to enter user mode and disable traps before entering the debugger. Add drRAND[...const0] to make FSDB have a harmless argument.

Fiala April 10, 1987 1:26:22 pm PST Moved the test that EU page fault is higher priority than EU stack overflow from GenSLimit to GenEUPageFault for Softcard debugging, so that the GenSLimit test will not run into page fault incompatibilities with the Softcard.

Load with "quad -cx GenDebugger GenTraps" and do "← LizardLiverImpl.careful ← FALSE" before execution. When simulated correctly with withSoftCard = TRUE, it terminates with HALT[177777B] at PC 4043607B, cycle 4758, Inst 1588. This diagnostic will NOT run under Lizard if DebuggerDefs.withSoftCard = TRUE because Lizard traps user mode writes to addresses < KernalLimit.

It tests the following machine functions (** means not tested because of some problem with the Lizard simulation):
1) User mode enabling and trap enabling and disabling via ifuYoungestL and RET to caller (L and the IFU stack were tested in GenReg.mesa).
2) KFC instruction.
3) Registers legal and illegal in User mode.
4) Instructions legal and illegal in User mode.
5) Verify that IFU stack overflow occurs when traps are enabled on DFC, SFC, SFCI, LFC, Xop1, Xop2, Xop3, Xop5, or KFC; on RBC, QBC, or BC that get bounds-check trap; on ADD that overflows; on LADD that gets NaN trap; on DUP that gets EU stack overflow; on RB[0] that gets an EU page fault; or on an ifu page fault (ifu page fault tested in GenTraps2); on user mode RADD that gets mode fault trap.
6) Verify that IFU stack overflow does not occur with 11 call stack entries on Jn, JB, JDB, JQB, JSR, JSD, or RET; on RBC, QBC, or BC that do not trap.
7) Verify that EU stack overflow trap occurs when traps are enabled and an instruction would put S in [SLimit .. SLimit + 16) for several opcodes that push the stack and for AS[n], ASL[n], and RET[n] (tested for only one value of SLimit).
8) Verify that EU stack overflow trap occurs when traps are enabled and an instruction would put S in [SLimit .. SLimit + 16) for several opcodes that pop the stack.
9) Verify that an EU stack overflow trap does not occur when ASL[n] makes S equal to SLimit - 1 or SLimit + 16 and does occur when ASL[n] makes S equal to SLimit or SLimit + 15 for SLimit = 1, 2, 4, 8, 16, 32, 64, and 111.
10) Verify that EU stack overflow is lower priority than bounds check, NaN, overflow, EU page fault, and mode fault.
11) Verify that IFU page fault occurs in sequence when jumping, calling, returning, conditionally jumping (correctly or incorrectly predicted), or falling through into an undeclared page.
12) Verify that IFU page fault does not occur when the untaken path of a conditional jump or conditional trap lies in an undeclared page.
13) Verify that EU page fault occurs in sequence for a storage read, a storage write, CST, and SFCI; that machine state which would have been affected by the faulting instruction is not modified, and that euMAR contains the fault address.
14) Verify that mode fault prevails over bounds check, overflow, NaN, and EU page fault traps.

15) **User mode and trap enabling and disabling via ifuEldestL aren't tested (don't need testing?).
16) **Memory access faults aren't tested, such as user mode WB into the Kernel (former Address Check tests were commented out because of architecture change); references to addresses >= 2^30 aren't tested (Lizard limitation).
17) **IFU page fault priority over EU stack overflow is not tested (see GenTraps2).
18) **IO Access faults on IOD, IODA, and ION aren't tested.
19) **Verify that EU stack overflow occurs with greater priority than an ALU trap caused on the instruction following a SIP which reenables interrupts.
20) **Verify that EU stack overflow occurs with greater priority than Reschedule following a SIP which reenables interrupts (tested in GenTraps2).
21) **EU write protect fault occurs in sequence for a storage write and the CST instruction, that machine state which would have been affected by the faulting instruction is not modified, and that euMAR contains the fault address. (Lizard doesn't simulate write protect faults.)
22) **Reschedule trap isn't tested because it is not simulated.

Basics USING [DoubleShiftLeft],

DebuggerDefs,

DragOpsCross USING [ProcessorRegister, XopBase, TrapBase, TrapWidthBytes, TrapIndex, Inst],
--Word, wordsPerPage, bytesPerWord, charsPerWord, bitsPerByte, bitsPerCharacter, bitsPerWord, bytesPerPage, logWordsPerPage, logBitsPerByte, logBitsPerChar, logBytesPerWord, logCharsPerWord, logBitsPerWord, logBytesPerPage, PageCount, PageNumber, maxPagesInVM, SixBitIndex, FiveBitIndex, TwoWords, FourBitIndex, Half, ThreeBitIndex, FourHalves, TwoHalves, Byte, ZerosByte, OnesByte, EightBytes, FourBytes, ByteIndex, BytesPerWord, TwoBytes, Comparison, ByteAddress, WordAddress, FieldDescriptor, RegIndex, PadByte, Lit8, Op4, Op8, JDist8, Inst, OIFormat, OQBformat, LRformat, QRformat, ShortRegQR, OBformat, LRBformat, RRformat, ODBformat, LRRBformat, RJBformat, ShortRegRJB, JBBformat, TrapWidthWords, TrapWidthBytes, XopBase, TrapBase, KernalLimit, TrapIndex, StackUnderflowTrap, IFUPageFaultTrap, ResetTrap, IFUStackOverflowTrap, EUStackOverflowTrap, RescheduleTrap, ALUCondFalse, ALUCondEZ, ALUCondLZ, ALUCondLE, ALUCondSpare, ALUCondNE, ALUCondGE, ALUCondGZ, ALUCondOver, ALUCondBC, ALUCondIL, ALUCondDO, ALUCondNotOver, ALUCondNB, ALUCondNI, ModeFault, MemAccessFault, IOAccessFault, EUPageFault, EUWriteFault, AUFault, euStack, euJunk, euToKBus, euMAR, euField, euConstant, euAux, euBogus, euLast, ifuYoungestL, ifuYoungestPC, ifuEldestL, ifuEldestPC, ifuSLimit, ifuBogus, ifuL, ifuS, ifuPC, ifuLast, EURegs, EULegalRegs, IFURegs, IFULegalRegs, StackedStatusWord, IFUStackIndex, IFUStackSize, IFUOverflow, EUStackIndex, EUStackSize, EULocalIndex, EULocals, EUAuxIndex, EUAuxRegs, EUConstIndex, EUConstants, IOLocation, ioRescheduleRequest, ioResetRequest, IOOperand, PCmdFormat, PCmdByteSelect, PCmdClass, PCmdSpace, PCmdDirection

DragOpsCrossUtils USING [CardToWord, FieldDescriptorToCard, IntToWord, CardToByte],
--InstToBytes, InstToFormat, BytePCToWordAddress, WordAddressToBytePC, IOOperandToCard, CardToIOOperand, FieldDescriptorToCard, CardToFieldDescriptor, BytesToWord, BytesToHalf, WordToBytes, HalfToBytes, HalvesToWord, WordToHalves, HighHalf, LowHalf, LeftHalf, RightHalf, SwapHalves, WordToInt, IntToWord, WordToCard, HalfToCard, ByteToCard, CardToWord, CardToHalf, CardToByte, DragAnd, DragOr, DragXor, DragNot, VanillaAdd, VanillaSub, AddDelta, HalfNot, HalfAnd, HalfOr, HalfXor, HalfShift, DoubleWordShiftLeft, SingleWordShiftLeft, SingleWordShiftRight, XopToBytePC, TrapIndexToBytePC, FieldUnit

HandCoding, --Has opcode and register defs.

HandCodingPseudos, --Label, SetLabel, GenLabel, GenLabelHere, UseLabel8A, UseLabel8B, UseLabel16, UseLabel32, LReg, PReg, SReg, AddReg, SubReg, SetRegConst, MoveReg, MoveRegI, LRegI, IndexedJump, ProcedureEntry, ProcedureExit, SetupField, ExtractField, ShiftLeft, LoadProcessorReg, StoreProcessorReg, CauseReschedule, CauseReset, GetSPLimit, SetSPLimit, GetYoungestPC, GetYoungestStatus, GetEldestPC, GetEldestStatus, SetYoungestPC, SetYoungestStatus, SetEldestPC, SetEldestStatus, Pause, Halt

HandCodingSupport; --Area, GetProc, PutProc, ProcList, NewArea, GenWithArea, Gen1WithArea, ForceOut, GetCurrentArea, LoadArea, GetOutputPC, SetOutputPC, WordAlign, ReserveData, OutputByte, OutputOneByte, OutputAlphaBeta, OutputAlphaBetaGammaDelta, OutputWord

IMPORTS Basics, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport

= BEGIN OPEN DebuggerDefs, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport;

ProcessorRegister: TYPE = DragOpsCross.ProcessorRegister;

ifuSLimit = 7-bit stack limit register. Any opcode which causes the stack pointer to enter the region [SLimit..SLimit+16) will be trapped to the EU stack overflow location.

ifuSLimit: CARDINAL = LOOPHOLE[ProcessorRegister.ifuSLimit, CARDINAL];

IFUStackSize = 15. LIP[ifuEldestPC] removes and SIP[ifuEldestPC] adds to the call stack.

ifuEldestPC: CARDINAL = LOOPHOLE[ProcessorRegister.ifuEldestPC, CARDINAL];

ifuEldestL: CARDINAL = LOOPHOLE[ProcessorRegister.ifuEldestL, CARDINAL];

ifuYoungestPC: CARDINAL = LOOPHOLE[ProcessorRegister.ifuYoungestPC, CARDINAL];

ifuYoungestL: CARDINAL = LOOPHOLE[ProcessorRegister.ifuYoungestL, CARDINAL];

euMAR: CARDINAL = LOOPHOLE[ProcessorRegister.euMAR, CARDINAL];

In this diagnostic, the auxiliary registers are called aux0 .. aux15; the locals reg0 .. reg15; and the constants const0 .. const11. Global register usage is as follows:
aux8 contains a code indicating the trap expected (0 if none).
const4 contains the constant 6 for trap routines.

aux0: AuxRegSpec = [aux[0]];

aux1: AuxRegSpec = [aux[1]];

aux2: AuxRegSpec = [aux[2]];

aux3: AuxRegSpec = [aux[3]];

aux4: AuxRegSpec = [aux[4]];

aux5: AuxRegSpec = [aux[5]];

aux6: AuxRegSpec = [aux[6]];

aux13: AuxRegSpec = [aux[13]];

aux14: AuxRegSpec = [aux[14]];

aux15: AuxRegSpec = [aux[15]];

const5: ConstSpec = [const[5]];

const6: ConstSpec = [const[6]];

const7: ConstSpec = [const[7]];

const8: ConstSpec = [const[8]];

const9: ConstSpec = [const[9]];

const10: ConstSpec = [const[10]];

const11: ConstSpec = [const[11]];

All: PROC = {

END.