GenSJ.mesa
Copyright © 1985, 1986, 1987 by Xerox Corporation. All rights reserved.
Edward Fiala February 7, 1986 1:46:58 pm PST
Curry, September 11, 1986 11:57:29 am PDT SJ => JSR.
Fiala November 6, 1986 9:01:56 am PST Cosmetic edits; added test for JSD.`
Fiala March 26, 1987 1:49:01 pm PST Change Reset, Pause, and Halt for operation with GenDebugger; put in withSoftCard conditional assembly to keep jumps within 1 megabyte.
Load with "quad -cx GenDebugger GenSJ". This diagnostic tests JSR (stack jump), JSD, SFC, and the 32 bits on the K bus path from the EU back to the IFU. When correctly executed, it terminates with a Halt[177777B] on instruction 154, cycle 1029, PC = 7770000B.
DIRECTORY
DebuggerDefs,
DragOpsCross USING [],
--Word, wordsPerPage, bytesPerWord, charsPerWord, bitsPerByte, bitsPerCharacter, bitsPerWord, bytesPerPage, logWordsPerPage, logBitsPerByte, logBitsPerChar, logBytesPerWord, logCharsPerWord, logBitsPerWord, logBytesPerPage, PageCount, PageNumber, maxPagesInVM, SixBitIndex, FiveBitIndex, TwoWords, FourBitIndex, Half, ThreeBitIndex, FourHalves, TwoHalves, Byte, ZerosByte, OnesByte, EightBytes, FourBytes, ByteIndex, BytesPerWord, TwoBytes, Comparison, ByteAddress, WordAddress, FieldDescriptor, RegIndex, PadByte, Lit8, Op4, Op8, JDist8, Inst, OIFormat, OQBformat, LRformat, QRformat, ShortRegQR, OBformat, LRBformat, RRformat, ODBformat, LRRBformat, RJBformat, ShortRegRJB, JBBformat, TrapWidthWords, TrapWidthBytes, XopBase, TrapBase, KernalLimit, TrapIndex, StackUnderflowTrap, IFUPageFaultTrap, ResetTrap, IFUStackOverflowTrap, EUStackOverflowTrap, RescheduleTrap, ALUCondFalse, ALUCondEZ, ALUCondLZ, ALUCondLE, ALUCondSpare, ALUCondNE, ALUCondGE, ALUCondGZ, ALUCondOver, ALUCondBC, ALUCondIL, ALUCondDO, ALUCondNotOver, ALUCondNB, ALUCondNI, ModeFault, MemAccessFault, IOAccessFault, EUPageFault, EUWriteFault, AUFault, euStack, euJunk, euToKBus, euMAR, euField, euConstant, euAux, euBogus, euLast, ifuYoungestL, ifuYoungestPC, ifuEldestL, ifuEldestPC, ifuSLimit, ifuBogus, ifuL, ifuS, ifuPC, ifuLast, EURegs, EULegalRegs, IFURegs, IFULegalRegs, StackedStatusWord, IFUStackIndex, IFUStackSize, IFUOverflow, EUStackIndex, EUStackSize, EULocalIndex, EULocals, EUAuxIndex, EUAuxRegs, EUConstIndex, EUConstants, IOLocation, ioRescheduleRequest, ioResetRequest, IOOperand, PCmdFormat, PCmdByteSelect, PCmdClass, PCmdSpace, PCmdDirection
DragOpsCrossUtils USING [CardToWord],
--InstToBytes, InstToFormat, BytePCToWordAddress, WordAddressToBytePC, IOOperandToCard, CardToIOOperand, FieldDescriptorToCard, CardToFieldDescriptor, BytesToWord, BytesToHalf, WordToBytes, HalfToBytes, HalvesToWord, WordToHalves, HighHalf, LowHalf, LeftHalf, RightHalf, SwapHalves, WordToInt, IntToWord, WordToCard, HalfToCard, ByteToCard, CardToWord, CardToHalf, CardToByte, DragAnd, DragOr, DragXor, DragNot, VanillaAdd, VanillaSub, AddDelta, HalfNot, HalfAnd, HalfOr, HalfXor, HalfShift, DoubleWordShiftLeft, SingleWordShiftLeft, SingleWordShiftRight, XopToBytePC, TrapIndexToBytePC, FieldUnit
HandCoding, --Has opcode and register defs.
HandCodingPseudos, --Label, SetLabel, GenLabel, GenLabelHere, UseLabel8A, UseLabel8B, UseLabel16, UseLabel32, LReg, PReg, SReg, AddReg, SubReg, SetRegConst, MoveReg, MoveRegI, LRegI, IndexedJump, ProcedureEntry, ProcedureExit, SetupField, ExtractField, ShiftLeft, LoadProcessorReg, StoreProcessorReg, CauseReschedule, CauseReset, GetSPLimit, SetSPLimit, GetYoungestPC, GetYoungestStatus, GetEldestPC, GetEldestStatus, SetYoungestPC, SetYoungestStatus, SetEldestPC, SetEldestStatus, Pause, Halt
HandCodingSupport; --Area, GetProc, PutProc, ProcList, NewArea, GenWithArea, Gen1WithArea, ForceOut, GetCurrentArea, LoadArea, GetOutputPC, SetOutputPC, WordAlign, ReserveData, OutputByte, OutputOneByte, OutputAlphaBeta, OutputAlphaBetaGammaDelta, OutputWord
GenSJ: CEDAR PROGRAM
IMPORTS DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport
= BEGIN OPEN DebuggerDefs, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport;
All: PROC = {
area: Area = GetCurrentArea[];
Exercises all PC adder bits with JSR = PC ← PC + [S].
GenJSR: PROC = {
DoJSR: PROC [destPC: LONG CARDINAL] = {
oldPC: LONG CARDINAL;
drLIQB[CardToWord[destPC]];
oldPC ← GetOutputPC[area];
drJSR[];
SetOutputPC[oldPC + destPC];
};
Exercise every bit position of the pc address; must avoid the vector for Xops and Traps and the debugger in byte positions [4000000B..4040000B). (DoJSR[d] changes the PC by d + 5 because of the 5 bytes in LIQB.) Initial PC is userBasePC = 4040000B.
IF withSoftCard THEN {
DoJSR[ 200001B]; --PC = 4240006B
DoJSR[ 400002B]; --PC = 4640015B
DoJSR[ 1000004B]; --PC = 5640026B
DoJSR[ 2000010B]; --PC = 7640043B
DoJSR[37774237730B]; --PC = 4100000B
DoJSR[ 20B]; --PC = 4100025B
DoJSR[ 40B]; --PC = 4100073B
DoJSR[ 100B]; --PC = 4100200B
DoJSR[ 200B]; --PC = 4100405B
DoJSR[ 400B]; --PC = 4101012B
DoJSR[ 1000B]; --PC = 4102017B
DoJSR[ 2000B]; --PC = 4104024B
DoJSR[ 4000B]; --PC = 4110031B
DoJSR[ 10000B]; --PC = 4120036B
DoJSR[ 20000B]; --PC = 4140043B
DoJSR[ 40000B]; --PC = 4200050B
DoJSR[ 100000B]; --PC = 4300055B
}
ELSE {
enterJSRTestPC: LONG CARDINAL = 2000B;
drJQB[CardToWord[enterJSRTestPC]];
SetOutputPC[enterJSRTestPC];
DoJSR[ 200040B]; --PC = 202045B
DoJSR[ 400100B]; --PC = 602152B
DoJSR[ 1000200B]; --PC = 1602357B
DoJSR[ 2000400B]; --PC = 3602764B
DoJSR[ 4001000B]; --PC = 7603771B
DoJSR[ 10002000B]; --PC = 17605776B
DoJSR[ 20004001B]; --PC = 37612004B
DoJSR[ 40010002B]; --PC = 77622013B
DoJSR[ 100020004B]; --PC = 177642024B
DoJSR[ 200040010B]; --PC = 377702041B
DoJSR[ 400100020B]; --PC = 1000002066B
DoJSR[ 1000000000B]; --PC = 2000002073B
DoJSR[ 2000000000B]; --PC = 4000002100B
DoJSR[ 4000000000B]; --PC = 10000002105B
DoJSR[10000000000B]; --PC = 20000002112B
DoJSR[20000000000B]; --PC = 2117B
};
};
Test JSD = PC ← [S].
GenJSD: PROC = {
DoJSD: PROC [destPC: LONG CARDINAL] = {
drLIQB[CardToWord[destPC]]; drJSD[]; SetOutputPC[destPC];
};
Exercise every bit position of the pc address; must avoid the vector for Xops and Traps and the debugger in byte positions [4000000B..4040000B).
IF withSoftCard THEN {
DoJSD[ 6000010B];
DoJSD[ 6000020B];
DoJSD[ 6000040B];
DoJSD[ 6000100B];
DoJSD[ 6000200B];
DoJSD[ 6000400B];
DoJSD[ 6001000B];
DoJSD[ 6002000B];
DoJSD[ 6404000B];
DoJSD[ 6010000B];
DoJSD[ 6020000B];
DoJSD[ 6040000B];
DoJSD[ 7100000B];
DoJSD[ 7200000B];
DoJSD[ 4450001B];
DoJSD[ 4460002B];
DoJSD[ 4470004B];
}
ELSE {
DoJSD[ 200200B];
DoJSD[ 400400B];
DoJSD[ 1001000B];
DoJSD[ 2002000B];
DoJSD[ 4004000B];
DoJSD[ 10010001B];
DoJSD[ 20020002B];
DoJSD[ 40040004B];
DoJSD[ 100100010B];
DoJSD[ 200200020B];
DoJSD[ 400400040B];
DoJSD[ 1001000100B];
DoJSD[ 2002000007B];
DoJSD[ 4004000125B];
DoJSD[10050000004B];
DoJSD[17060000234B];
};
};
GenSFC: PROC = {
Define procedure for putting out a SFC opcode. Page creation automatically fills the unused bytes in each page with 0, so a trap will happen if a wild jump or non-jump occurs.
DoSFC: PROC [destPC: LONG CARDINAL] ~ {
drADDB[200B];
drLIQB[CardToWord[destPC]];
drSFC[];
drADDB[1];
drRETN[];
SetOutputPC[destPC];
};
enterSFCTestPC: LONG CARDINAL = 1774000B * bytesPerWord;
endTestPC: LONG CARDINAL = 1776000B * bytesPerWord;
firstJumpPC: LONG CARDINAL = IF withSoftCard THEN 5000000B ELSE 400100B;
okSFC: Label = GenLabel[];
drJQB[CardToWord[enterSFCTestPC]];
SetOutputPC[enterSFCTestPC];
Exercise every bit position of the pc address; must avoid the vector for Xops and Traps and the debugger in byte positions [4000000B..4040000B).
drLIB[0]; --Counter used to verify that the calls and returns have occurred.
drLIQB[CardToWord[firstJumpPC]];
drSFC[];
drLIQB[CardToWord[3416B]];
drRJEB[popSrc, belowSrcPop, UseLabel8B[okSFC]];
Pause[];
SetLabel[okSFC];
drJQB[CardToWord[endTestPC]];
SetOutputPC[firstJumpPC];
IF withSoftCard THEN { --1 megabyte limit confines PC to [4,000,000B..10,000,000B).
DoSFC[ 5010020B]; --[s] = 200B after the SFC, 3416B after the RETN
DoSFC[ 5020040B]; --[s] = 400B after the SFC, 3415B after the RETN
DoSFC[ 5040100B]; --[s] = 600B after the SFC, 3414B after the RETN
DoSFC[ 5100200B]; --[s] = 1000B after the SFC, 3413B after the RETN
DoSFC[ 5200400B]; --[s] = 1200B after the SFC, 3412B after the RETN
DoSFC[ 5401000B]; --[s] = 1400B after the SFC, 3411B after the RETN
DoSFC[ 6202000B]; --[s] = 1600B after the SFC, 3410B after the RETN
DoSFC[ 6004001B]; --[s] = 2000B after the SFC, 3407B after the RETN
DoSFC[ 4060002B]; --[s] = 2200B after the SFC, 3406B after the RETN
DoSFC[ 4070004B]; --[s] = 2400B after the SFC, 3405B after the RETN
DoSFC[ 5100010B]; --[s] = 2600B after the SFC, 3404B after the RETN
DoSFC[ 4200020B]; --[s] = 3000B after the SFC, 3403B after the RETN
DoSFC[ 4400040B]; --[s] = 3200B after the SFC, 3402B after the RETN
DoSFC[ 4677777B]; --[s] = 3400B after the SFC, 3401B after the RETN
}
ELSE {
DoSFC[ 1000200B]; --[s] = 200B after the SFC, 3416B after the RETN
DoSFC[ 2000400B]; --[s] = 400B after the SFC, 3415B after the RETN
DoSFC[ 4010000B]; --[s] = 600B after the SFC, 3414B after the RETN
DoSFC[ 10002000B]; --[s] = 1000B after the SFC, 3413B after the RETN
DoSFC[ 20004001B]; --[s] = 1200B after the SFC, 3412B after the RETN
DoSFC[ 40001002B]; --[s] = 1400B after the SFC, 3411B after the RETN
DoSFC[ 100020004B]; --[s] = 1600B after the SFC, 3410B after the RETN
DoSFC[ 200040010B]; --[s] = 2000B after the SFC, 3407B after the RETN
DoSFC[ 400100020B]; --[s] = 2200B after the SFC, 3406B after the RETN
DoSFC[ 1000000000B]; --[s] = 2400B after the SFC, 3405B after the RETN
DoSFC[ 2000000000B]; --[s] = 2600B after the SFC, 3404B after the RETN
DoSFC[ 4000000000B]; --[s] = 3000B after the SFC, 3403B after the RETN
DoSFC[10000000000B]; --[s] = 3200B after the SFC, 3402B after the RETN
DoSFC[20000200040B]; --[s] = 3400B after the SFC, 3401B after the RETN
};
drRETN[];
SetOutputPC[endTestPC];
};
Begin at PC = userBasePC = 1010000B * 4, L = 1, S = 0 as established in GenDebugger.
GenJSR[];
GenJSD[];
GenSFC[];
Halt[177777B]; --Terminate here at the end of the program
};
END.