[Indigo]<Dragon>Diagnostics>GenRW.mesa!8

GenRW.mesa

Edward Fiala February 7, 1986 1:03:42 pm PST

Curry, September 11, 1986 11:41:17 pm PDT

Curry, September 11, 1986 11:40:46 pm PDT const2 => const7

Fiala November 5, 1986 6:04:33 pm PST Cosmetic edits.

Fiala March 27, 1987 2:57:10 pm PST Eliminate Reset, Halt, and Pause stuff
to run with GenDebugger; eliminate FillXop, FillTrap, and entry labels; do not do GenCST when withSoftCard = TRUE; add massiveTesting conditional.

Load with "quad -cx GenDebugger GenRW". This diagnostic tests P bus data and addressing and all opcodes which read or write memory. When correctly executed with DebuggerDefs.massiveTesting = TRUE and withSoftCard = TRUE, it terminates with a HALT[177777b] at PC = 4050713B on instruction 1292 cycle 4101. When correctly executed with DebuggerDefs.massiveTesting = FALSE, it terminates with a HALT[177777b] at PC = ? on instruction ? cycle ?.

**Since Lizard requires byte addresses, the top two memory address bits cannot be tested.

DIRECTORY

Basics USING [DoubleShiftLeft],

DebuggerDefs,

DragOpsCross USING [],
--Word, wordsPerPage, bytesPerWord, charsPerWord, bitsPerByte, bitsPerCharacter, bitsPerWord, bytesPerPage, logWordsPerPage, logBitsPerByte, logBitsPerChar, logBytesPerWord, logCharsPerWord, logBitsPerWord, logBytesPerPage, PageCount, PageNumber, maxPagesInVM, SixBitIndex, FiveBitIndex, TwoWords, FourBitIndex, Half, ThreeBitIndex, FourHalves, TwoHalves, Byte, ZerosByte, OnesByte, EightBytes, FourBytes, ByteIndex, BytesPerWord, TwoBytes, Comparison, ByteAddress, WordAddress, FieldDescriptor, RegIndex, PadByte, Lit8, Op4, Op8, JDist8, Inst, OIFormat, OQBformat, LRformat, QRformat, ShortRegQR, OBformat, LRBformat, RRformat, ODBformat, LRRBformat, RJBformat, ShortRegRJB, JBBformat, TrapWidthWords, TrapWidthBytes, XopBase, TrapBase, KernalLimit, TrapIndex, StackUnderflowTrap, IFUPageFaultTrap, ResetTrap, IFUStackOverflowTrap, EUStackOverflowTrap, RescheduleTrap, ALUCondFalse, ALUCondEZ, ALUCondLZ, ALUCondLE, ALUCondSpare, ALUCondNE, ALUCondGE, ALUCondGZ, ALUCondOver, ALUCondBC, ALUCondIL, ALUCondDO, ALUCondNotOver, ALUCondNB, ALUCondNI, ModeFault, MemAccessFault, IOAccessFault, EUPageFault, EUWriteFault, AUFault, euStack, euJunk, euToKBus, euMAR, euField, euConstant, euAux, euBogus, euLast, ifuYoungestL, ifuYoungestPC, ifuEldestL, ifuEldestPC, ifuSLimit, ifuBogus, ifuL, ifuS, ifuPC, ifuLast, EURegs, EULegalRegs, IFURegs, IFULegalRegs, StackedStatusWord, IFUStackIndex, IFUStackSize, IFUOverflow, EUStackIndex, EUStackSize, EULocalIndex, EULocals, EUAuxIndex, EUAuxRegs, EUConstIndex, EUConstants, IOLocation, ioRescheduleRequest, ioResetRequest, IOOperand, PCmdFormat, PCmdByteSelect, PCmdClass, PCmdSpace, PCmdDirection

DragOpsCrossUtils USING [CardToWord],
--InstToBytes, InstToFormat, BytePCToWordAddress, WordAddressToBytePC, IOOperandToCard, CardToIOOperand, FieldDescriptorToCard, CardToFieldDescriptor, BytesToWord, BytesToHalf, WordToBytes, HalfToBytes, HalvesToWord, WordToHalves, HighHalf, LowHalf, LeftHalf, RightHalf, SwapHalves, WordToInt, IntToWord, WordToCard, HalfToCard, ByteToCard, CardToWord, CardToHalf, CardToByte, DragAnd, DragOr, DragXor, DragNot, VanillaAdd, VanillaSub, AddDelta, HalfNot, HalfAnd, HalfOr, HalfXor, HalfShift, DoubleWordShiftLeft, SingleWordShiftLeft, SingleWordShiftRight, XopToBytePC, TrapIndexToBytePC, FieldUnit

HandCoding, --Has opcode and register defs.

HandCodingPseudos, --Label, SetLabel, GenLabel, GenLabelHere, UseLabel8A, UseLabel8B, UseLabel16, UseLabel32, LReg, PReg, SReg, AddReg, SubReg, SetRegConst, MoveReg, MoveRegI, LRegI, IndexedJump, ProcedureEntry, ProcedureExit, SetupField, ExtractField, ShiftLeft, LoadProcessorReg, StoreProcessorReg, CauseReschedule, CauseReset, GetSPLimit, SetSPLimit, GetYoungestPC, GetYoungestStatus, GetEldestPC, GetEldestStatus, SetYoungestPC, SetYoungestStatus, SetEldestPC, SetEldestStatus, Pause, Halt

HandCodingSupport; --Area, GetProc, PutProc, ProcList, NewArea, GenWithArea, Gen1WithArea, ForceOut, GetCurrentArea, LoadArea, GetOutputPC, SetOutputPC, WordAlign, ReserveData, OutputByte, OutputOneByte, OutputAlphaBeta, OutputAlphaBetaGammaDelta, OutputWord

GenRW: CEDAR PROGRAM

IMPORTS Basics, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport

= BEGIN OPEN DebuggerDefs, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport;

In this diagnostic, the auxiliary registers are called aux0, aux1, ..., aux15; the locals are called reg0, reg1, ..., reg15; and the constants are called const0, const1, ..., const15.
const7 contains -1.

aux0: AuxRegSpec = [aux[0]];

aux1: AuxRegSpec = [aux[1]];

aux2: AuxRegSpec = [aux[2]];

aux3: AuxRegSpec = [aux[3]];

aux4: AuxRegSpec = [aux[4]];

aux5: AuxRegSpec = [aux[5]];

aux6: AuxRegSpec = [aux[6]];

aux14: AuxRegSpec = [aux[14]];

aux15: AuxRegSpec = [aux[15]];

const5: ConstSpec = [const[5]];

const6: ConstSpec = [const[6]];

const7: ConstSpec = [const[7]];

const8: ConstSpec = [const[8]];

const9: ConstSpec = [const[9]];

const10: ConstSpec = [const[10]];

const11: ConstSpec = [const[11]];

All: PROC = {

area: Area = GetCurrentArea[];

The Lizard simulator requires that all storage touched by a program be declared in advance; for data areas touched by EU memory references, this procedure is used to declare words that will be touched. **Maybe Lizard requires only that each page touched by a program be reserved by a single OutputWord??

ReserveSpace: PROC [addr, nwords: CARD] = {

oldPC: LONG CARDINAL = GetOutputPC[area];

bytePC: LONG CARDINAL ← Basics.DoubleShiftLeft[[lc[addr]], 2].lc;

SetOutputPC[bytePC]; --pc is a byte address

FOR I: CARD IN [0..nwords) DO

OutputWord[area, CardToWord[0], FALSE];

ENDLOOP;

SetOutputPC[oldPC];

};

Test P bus data by writing data values with each bit in 0 and 1 states.

GenData: PROC [] ~ {

**Need code to setup the map for the references here somewhere.

wval: LONG CARDINAL ← 1;

baseAddr: LONG CARDINAL ← 1400000B;

ReserveSpace[baseAddr, 32];

drLIQB[CardToWord[baseAddr]]; --reg0 ← base register for writes and reads

FOR I: CARDINAL IN [0..32) DO

drLIQB[CardToWord[wval]];

wval ← Basics.DoubleShiftLeft[[lc[wval]], 1].lc;

drSRIn[reg0, I];

ENDLOOP;

wval ← 1;

FOR I: CARDINAL IN [0..32) DO

rdOK: Label = GenLabel[];

drLRIn[reg0, I];

drLIQB[CardToWord[wval]];

wval ← Basics.DoubleShiftLeft[[lc[wval]], 1].lc;

drRJEBJ[popSrc, belowSrcPop, UseLabel8B[rdOK]]; Pause[]; SetLabel[rdOK];

ENDLOOP;

drASL[377B]; --Clear the stack

};

Test P bus addressing by writing at addresses with each address bit in 0 and 1 states.

GenAddr: PROC [] ~ {

wval: LONG CARDINAL ← 1;

baseAddr: LONG CARDINAL = 1400000B;

upperDisp: CARDINAL = IF withSoftCard THEN 17 ELSE 30;

FOR I: CARDINAL IN [0..upperDisp) DO

ReserveSpace[baseAddr + wval, 1];

drLIQB[CardToWord[wval + baseAddr]]; --reg0 ← memory reference address

wval ← Basics.DoubleShiftLeft[[lc[wval]], 1].lc;

drLIB[I];

drSRIn[reg0, 0];

drDIS[];

ENDLOOP;

wval ← 1;

drLIQB[CardToWord[baseAddr]]; --reg0 ← base address

FOR I: CARDINAL IN [0..upperDisp) DO

rdOK: Label = GenLabel[];

drLIQB[CardToWord[wval]];

wval ← Basics.DoubleShiftLeft[[lc[wval]], 1].lc;

drRRX[topDst, reg0, topSrc];

drJEBBJ[I, UseLabel8B[rdOK]]; Pause[]; SetLabel[rdOK];

ENDLOOP;

drASL[377B]; --Clear the stack

};

GenRWAll: PROC [] ~ {

139 instructions tests all the memory writes and reads by first writing at addresses just above baseAddr using all the different memory write opcodes and then reading back the values using all the memory read opcodes and testing the data.

RWTest: PROC [baseAddr, dval: LONG CARDINAL] ~ {

LRI0ok: Label = GenLabel[];

LRI13ok: Label = GenLabel[];

RRIok: Label = GenLabel[];

ReadBackBad: Label = GenLabel[];

ReadBackBad1: Label = GenLabel[];

ReadBackBad2: Label = GenLabel[];

dvalx: LONG CARDINAL ← dval;

ReserveSpace[baseAddr, 42];

FOR I: CARDINAL IN [0..16) DO

drLIQB[CardToWord[baseAddr + LONG[I]]];

ENDLOOP;

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg0, 0]; --baseAddr

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg1, 1]; --baseAddr + 2

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg2, 2]; --baseAddr + 4

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg3, 3]; --baseAddr + 6

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg4, 4]; --baseAddr + 8

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg5, 5]; --baseAddr + 10

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg6, 6]; --baseAddr + 12

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg7, 7]; --baseAddr + 14

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg8, 8]; --baseAddr + 16

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg9, 9]; --baseAddr + 18

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg10, 10]; --baseAddr + 20

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg11, 11]; --baseAddr + 22

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg12, 12]; --baseAddr + 24

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg13, 13]; --baseAddr + 26

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg14, 14]; --baseAddr + 28

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1; drSRIn[reg15, 15]; --baseAddr + 30

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1;

drLIQB[CardToWord[baseAddr + 16]];

drWB[16]; --baseAddr + 32

drLIQB[CardToWord[baseAddr + 17]];

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1;

drWSB[17]; --baseAddr + 34

drLIQB[CardToWord[baseAddr + 18]];

drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1;

drPSB[18]; --baseAddr + 36

drDIS[];

dvalx ← dval;

drLRIn[reg0, 0]; drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1;

drRJEBJ[popSrc, belowSrcPop, UseLabel8B[LRI0ok]]; SetLabel[ReadBackBad]; Pause[]; SetLabel[LRI0ok];

drLRIn[reg1, 1]; drLIQB[CardToWord[dvalx]]; dvalx ← dvalx + 1;