DBusImpl.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Barth, November 14, 1986 5:49:52 pm PST
DIRECTORY CoreClasses, CoreCreate, CoreFlat, CoreProperties, DBus, Logic, Ports, Rosemary;
DBusImpl: CEDAR PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreProperties, Logic, Ports, Rosemary
EXPORTS DBus
= BEGIN OPEN DBus;
Cells
ConstantName: ROPE = Rosemary.Register[roseClassName: "Constant", init: ConstantInit, evalSimple: ConstantSimple];
ConstantState: TYPE = REF ConstantStateRec;
ConstantStateRec: TYPE = RECORD [
out: NATLAST[NAT],
val: LONG CARDINAL];
ConstantInit: Rosemary.InitProc = {
state: ConstantState ← NEW[ConstantStateRec];
{OPEN state;
[out] ← Ports.PortIndexes[cellType.public, "Output"];
val ← NARROW[CoreProperties.GetCellTypeProp[cellType, $value], REF LONG CARDINAL]^;
Ports.LCToLS[val, p[out].ls]};
stateAny ← state;
};
ConstantSimple: Rosemary.EvalProc = {
state: ConstantState ← NARROW[stateAny];
{OPEN state; Ports.LCToLS[val, p[out].ls]};
};
SoftConstant: PUBLIC PROC [b: NAT, v: INT] RETURNS [ct: CellType] = {
ct ← CoreClasses.CreateUnspecified[name: ConstantName, public: CoreCreate.Wires["Vdd", "Gnd", CoreCreate.Seq["Output", b]]];
CoreProperties.PutCellTypeProp[ct, $value, NEW[LONG CARDINALLOOPHOLE[v]]];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: ConstantName];
[] ← CoreFlat.CellTypeCutLabels[ct, Logic.logicCutSet];
Ports.InitPorts[ct, l, none, "Vdd", "Gnd"];
Ports.InitPorts[ct, ls, drive, "Output"];
};
FirmConstant: PUBLIC PROC [b: NAT, v: INT] RETURNS [ct: CellType] = {
ct ← CoreClasses.CreateUnspecified[name: ConstantName, public: CoreCreate.Wires["Vdd", "Gnd", CoreCreate.Seq["Output", b], "DOut", "DIn"]]; -- Fix to make DOut high order bit of Output
CoreProperties.PutCellTypeProp[ct, $value, NEW[LONG CARDINALLOOPHOLE[v]]];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: ConstantName];
[] ← CoreFlat.CellTypeCutLabels[ct, Logic.logicCutSet];
Ports.InitPorts[ct, l, none, "Vdd", "Gnd"];
Ports.InitPorts[ct, ls, drive, "Output"];
};
HardConstant: PUBLIC PROC [b: NAT, v: INT] RETURNS [ct: CellType] = {
ct ← CoreClasses.CreateUnspecified[name: ConstantName, public: CoreCreate.Wires["Vdd", "Gnd", CoreCreate.Seq["Output", b], "DOut", "DIn", "Shift", "Execute"]]; -- Fix to make DOut high order bit of Output
CoreProperties.PutCellTypeProp[ct, $value, NEW[LONG CARDINALLOOPHOLE[v]]];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: ConstantName];
[] ← CoreFlat.CellTypeCutLabels[ct, Logic.logicCutSet];
Ports.InitPorts[ct, l, none, "Vdd", "Gnd"];
Ports.InitPorts[ct, ls, drive, "Output"];
};
Wiring
WireDBusGivenOrder: PUBLIC PROC [root: CellType, busName: ROPE, order: Order] = {
};
WireDBusComputeOrder: PUBLIC PROC [root: CellType, busName: ROPE] RETURNS [order: Order] = {
};
Order Operations
OrderSize: PUBLIC PROC [order: Order] RETURNS [size: NAT] = {
};
OrderIndex: PUBLIC PROC [order: Order, bit: FlatCellType] RETURNS [index: NAT] = {
};
WriteOrder: PUBLIC PROC [order: Order, fileName: ROPE] = {
};
ReadOrder: PUBLIC PROC [fileName: ROPE] RETURNS [order: Order] = {
};
END.