DBusConnect.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Barth, November 14, 1986 2:49:12 pm PST
DIRECTORY Core, CoreFlat;
DBusConnect: CEDAR DEFINITIONS = BEGIN
Theory
This program adds the proper wires to a Core structure so that a DBus is properly wired.
Treats any cell type having the property $DBusData as a leaf state cell. If the wires referenced by DBusDataRec are not already public they will be added to the public of the leaf state cell.
A cell type having the property $DBusControl must be reachable from the root cell type. This cell must have the property $DBusData.
This program wires the control wire of DBusControl to the control wire of all leaf state cells.
If no order is supplied then the program wires the out wire of DBusControl to the in wire of the first leaf state cell it finds, the out wire of the first leaf state cell it finds to the in wire of the next leaf state cell it finds and so on until there are no more leaf state cells at which time it wires the out wire of the last leaf state cell to the in wire of DBusControl. If there are no leaf state cells then it wires the out wire of DBusControl to the in wire of DBusControl. Adds all the public and internal wires necessary to accomplish the job.
If an order is supplied then the program wires the leaf state cells in the order of the order list.
What about prewired portions of a DBus?
What about portions of the diagram prewired by the standard cell system, i.e. partial orders supplied?
Perhaps this program should get into the act between placement and routing.
Types
ROPE: TYPE = Core.ROPE;
Wire: TYPE = Core.Wire;
CellType: TYPE = Core.CellType;
FlatCellType: TYPE = CoreFlat.FlatCellType;
Order: TYPE = CoreFlat.FlatCellTypes;
DBusData: TYPE = REF DBusDataRec;
DBusDataRec: TYPE = RECORD [
name: ROPE ← NIL,
control: Wire ← NIL,
in: Wire ← NIL,
out: Wire ← NIL];
Wiring
WireDBusGivenOrder: PROC [root: CellType, busName: ROPE, order: Order];
The cells in the order list are wired into a DBus. The value of the DBusName and DBusControl atoms are checked against busName. If they are not Rope.Equal then an error message is issued.
WireDBusComputeOrder: PROC [root: CellType, busName: ROPE] RETURNS [order: Order];
busName determines which DBusControl cell type to use for the root of the DBus and to select which leaf state cells are to be wired into the bus. Returns a list which specifies the order in which they were wired.
Order Operations
OrderSize: PROC [order: Order] RETURNS [index: NAT];
Returns the number of bits in the order.
OrderIndex: PROC [order: Order, bit: FlatCellType] RETURNS [index: NAT];
Map from logical bit to bit position within the order.
WriteOrder: PROC [order: Order, fileName: ROPE];
Write an order into a file.
ReadOrder: PROC [fileName: ROPE] RETURNS [order: Order];
Read an order from a file.
END.