
    <<CrossRAMTest.mesa>>
        <<Barth, November 1, 1985 6:27:50 pm PST>>

    DIRECTORY CrossRAM, Rosemary;

    CrossRAMTest: CEDAR PROGRAM
        IMPORTS Rosemary =
        BEGIN OPEN CrossRAM;

    Write2Read2: Rosemary.CellTestProc = {
    AccessRAM: PROC [write: BOOL, address: CARDINAL, data: CARDINAL] = {
    p[Address].c _ address;
    <<>>
    <<precharge>>
    p[nPrecharge].b _ FALSE;
    Eval[];
    p[nPrecharge].b _ TRUE;
    Eval[];
    <<>>
    <<enable select line>>
    p[Access].b _ TRUE;
    <<>>
    <<if write then enable write drivers>>
    IF write THEN {
    p[Data].d _ force;
    p[Write].b _ TRUE;
    } ELSE {
    p[Data].d _ expect;
    p[Read].b _ TRUE;
    };
    p[Data].c _ data;
    Eval[];
    <<>>
    <<disable select line>>
    p[Access].b _ p[Write].b _ p[Read].b _ FALSE;
    <<>>
    p[Data].d _ none;

    Eval[];
    };

    p[Vdd].b _ TRUE; p[Gnd].b _ FALSE;
    p[Vdd].d _ force; p[Gnd].d _ force;
    p[Vdd].type _ b; p[Gnd].type _ b;

    p[PadVdd].b _ TRUE; p[PadGnd].b _ FALSE;
    p[PadVdd].d _ force; p[PadGnd].d _ force;
    p[PadVdd].type _ b; p[PadGnd].type _ b;

    p[nPrecharge].b _ TRUE; p[Access].b _ FALSE;
    p[nPrecharge].d _ force; p[Access].d _ force;
    p[nPrecharge].type _ b; p[Access].type _ b;

    p[Write].b _ FALSE; p[Read].b _ FALSE;
    p[Write].d _ force; p[Read].d _ force;
    p[Write].type _ b; p[Read].type _ b;

    p[Address].d _ force;
    p[Address].type _ c;
        FOR port: NAT IN [0..p[Address].size) DO
            p[Address][port].type _ sub;
            ENDLOOP;
    p[Data].d _ none;
    p[Data].type _ c;
        FOR port: NAT IN [0..p[Data].size) DO
            p[Data][port].type _ sub;
            ENDLOOP;
    Eval[! Rosemary.Stop => RESUME];
    AccessRAM[write: TRUE, address: 0, data: 0];
    AccessRAM[write: TRUE, address: 1, data: LAST[CARDINAL]];
    AccessRAM[write: FALSE, address: 0, data: 0];
    AccessRAM[write: FALSE, address: 1, data: LAST[CARDINAL]];
        };

    Rosemary.RegisterTest[testName: "Write2Read2", testProc: Write2Read2];

    END.