CrossRAMRAM.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, November 7, 1985 4:43:48 pm PST
Louis Monier October 23, 1985 6:35:23 pm PDT
Bertrand Serlet December 6, 1985 1:55:53 pm PST
DIRECTORY CoreCompose, CoreFlatten, CoreProperties, IO, PWCore, Rope, Rosemary, Sinix;
CrossRAMRAM:
CEDAR
PROGRAM
IMPORTS CoreCompose, CoreFlatten, CoreProperties, IO, PWCore, Rope, Rosemary, Sinix =
BEGIN OPEN CoreCompose;
columnOcts, rowQuads: INT, static: BOOL
RAMArray:
ROPE = RegisterStructureProc[name: "RAMArray", proc: CreateRAMArray];
CreateRAMArray: StructureProc = {
static, dynamic: InstanceRec;
PushBool[context, $static, TRUE];
static ← [actual: "Vdd: Vdd[start: 0, len: rowQuads], Word: Word[start: 0, len: 2*rowQuads]",
type: CreateStructure[name: SubArray, context: context]];
PushBool[context, $static, FALSE];
dynamic ← [actual: "Vdd: Vdd[start: rowQuads, len: rowQuads], Word: Word[start: 2*rowQuads, len: 2*rowQuads]",
type: CreateStructure[name: SubArray, context: context]];
cellType ← CreateRecordCell[
name: RAMArray,
context: context,
public: CreateWires[context,
"Vdd[seq: 2*rowQuads], Gnd, Word[seq: 4*rowQuads], Bit[seq: 8*columnOcts], nBit[seq: 8*columnOcts]"],
instances: LIST [static, dynamic]];
IF GetBool[context, $PWCore] THEN PWCore.SetAbutY[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.Extract[PWCore.GetLayout[cellType]];
};
columnOcts, rowQuads: INT
Ports: Gnd, Word[0..2*rowQuads), Bit[0..8*columnOcts), nBit[0..8*columnOcts), IF static THEN Vdd[0..rowQuads)
SubArray:
ROPE = RegisterStructureProc[name: "SubArray", proc: CreateSubArray];
CreateSubArray: StructureProc = {
static: BOOL ← GetBool[context, $static];
rowQuads: INT ← GetInt[context, $rowQuads];
cellType ← CreateSequenceCell[
name: IF static THEN "SSubArray" ELSE "DSubArray",
baseCell: CreateStructure[name: RamRow, context: context],
count: rowQuads,
sequencePorts: Rope.Cat["Word",
IF static THEN ", Vdd" ELSE NIL
", Vdd"
]
];
IF GetBool[context, $Rosemary] THEN Rosemary.Bind[cellType: cellType, roseClassName: SubArrayRoseClass];
CoreProperties.PutCellTypeProp[on: cellType, prop: CoreFlatten.CoreFlattenCutSets, value: LIST["JustAboveTransistors"]];
IF GetBool[context, $PWCore] THEN PWCore.SetArrayY[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.Extract[PWCore.GetLayout[cellType]];
};
SubArrayRoseClass: ROPE = Rosemary.Register[roseClassName: SubArray, init: SubArrayInit, evalSimple: SubArraySimple];
SubArrayGnd: NAT = 0;
SubArrayWord: NAT = 1;
SubArrayBit: NAT = 2;
SubArraynBit: NAT = 3;
SubArrayVdd: NAT = 4;
SubArrayState: TYPE = REF SubArrayStateRec;
SubArrayStateRec:
TYPE =
RECORD [
static: BOOL,
bits: SEQUENCE row: NAT OF SubArrayRow];
SubArrayRow: TYPE = REF SubArrayRowRec;
SubArrayRowRec:
TYPE =
RECORD [
bits: SEQUENCE column: NAT OF SubArrayBitRec];
SubArrayBitRec:
TYPE =
RECORD [
bit: BOOL ← FALSE,
nbit: BOOL ← TRUE];
SubArrayInit: Rosemary.InitProc = {
state: SubArrayState;
p[SubArrayGnd].type ← b;
FOR port:
NAT
IN [0..p[SubArrayWord].size)
DO
p[SubArrayWord][port].type ← b;
ENDLOOP;
FOR port:
NAT
IN [0..p[SubArrayBit].size)
DO
p[SubArrayBit][port].type ← b;
p[SubArraynBit][port].type ← b;
ENDLOOP;
state ← NEW[SubArrayStateRec[p[SubArrayWord].size]];
state.static ← p.size>4;
IF state.static
THEN
FOR port:
NAT
IN [0..p[SubArrayVdd].size)
DO
p[SubArrayVdd][port].type ← b;
ENDLOOP;
FOR row:
NAT
IN [0..p[SubArrayBit].size)
DO
state[row] ← NEW[SubArrayRowRec[p[SubArrayBit].size]];
ENDLOOP;
stateAny ← state;
};
SubArraySimple: Rosemary.EvalProc = {
state: SubArrayState ← NARROW[stateAny];
row: NAT;
foundActive: BOOL ← FALSE;
IF p[SubArrayGnd].b THEN SIGNAL Rosemary.Stop[];
IF state.static
THEN
FOR port:
NAT
IN [0..p[SubArrayVdd].size)
DO
IF NOT p[SubArrayVdd][port].b THEN SIGNAL Rosemary.Stop[];
ENDLOOP;
FOR port:
NAT
IN [0..p[SubArrayWord].size)
DO
IF p[SubArrayWord][port].b
THEN {
IF foundActive THEN SIGNAL Rosemary.Stop[];
foundActive ← TRUE;
row ← port;
};
ENDLOOP;
IF foundActive
THEN {
FOR column:
NAT
IN [0..p[SubArrayBit].size)
DO
state[row][column].bit ← IF state[row][column].nbit THEN FALSE ELSE p[SubArrayBit][column].b;
state[row][column].nbit ← IF state[row][column].bit THEN FALSE ELSE p[SubArraynBit][column].b;
state[row][column].bit ← IF state[row][column].nbit THEN FALSE ELSE p[SubArrayBit][column].b;
p[SubArrayBit][column].d ← IF state[row][column].nbit THEN drive ELSE IF state.static THEN driveWeak ELSE none;
p[SubArrayBit][column].b ← state[row][column].bit;
p[SubArraynBit][column].d ← IF state[row][column].bit THEN drive ELSE IF state.static THEN driveWeak ELSE none;
p[SubArraynBit][column].b ← state[row][column].nbit;
ENDLOOP;
}
ELSE {
FOR port:
NAT
IN [0..p[SubArrayBit].size)
DO
p[SubArrayBit][port].d ← none;
p[SubArraynBit][port].d ← none;
ENDLOOP;
};
};
Ports: Gnd, Word[0..2), Bit[0..8*columnOcts), nBit[0..8*columnOcts), IF static THEN Vdd
RamRow:
ROPE = RegisterStructureProc[name: "RamRow", proc: CreateRAMRow];
CreateRAMRow: StructureProc = {
static: BOOL ← GetBool[context, $static];
columnOcts: INT ← GetInt[context, $columnOcts];
cellType ← CreateSequenceCell[
name: IO.PutFR["%g*%g", IF static THEN IO.rope["SRamRow"] ELSE IO.rope["DRamRow"], IO.int[columnOcts]],
baseCell: CreateStructure[name: RamOctStitch, context: context],
count: columnOcts,
sequencePorts: "Bit, nBit"];
IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.Extract[PWCore.GetLayout[cellType]];
};
Ports: Gnd, Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd
RamOctStitch:
ROPE = RegisterStructureProc[name: "RamOctStitch", proc: CreateRAMOctStitch];
CreateRAMOctStitch: StructureProc = {
static: BOOL ← GetBool[context, $static];
cellType ← CreateRecordCell[
name: IF static THEN "SRamOctStitch" ELSE "DRamOctStitch",
context: context,
public: CreateWires[context, Rope.Cat[
"Gnd, Word[seq: 2], Bit[seq: 8], nBit[seq: 8]",
", Vdd"
IF static THEN ", Vdd" ELSE NIL
]],
instances:
LIST [
[type: CreateStructure[name: "RamOct", context: context], actual: "Gnd: [Gnd, Gnd]"],
[type: CreateStructure[name: "RamStitch", context: context]]]];
IF GetBool[context, $PWCore] THEN PWCore.SetAbutX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.Extract[PWCore.GetLayout[cellType]];
};
Ports: Gnd[0..2), Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd
RamOct:
ROPE = RegisterStructureProc[name: "RamOct", proc: CreateRAMOct];
CreateRAMOct: StructureProc = {
static: BOOL ← GetBool[context, $static];
cellType ← CreateSequenceCell[
name: IF static THEN "SRamOct" ELSE "DRamOct",
baseCell: CreateStructure[name: "RamTwoBits", context: context],
count: 8,
sequencePorts: "Bit, nBit"];
IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.Extract[PWCore.GetLayout[cellType]];
};
Ports: Gnd[0..2), Word[0..2), Bit, nBit, IF static THEN Vdd
RamTwoBits:
ROPE = RegisterStructureProc[name: "RamTwoBits", proc: CreateRAMTwoBits];
CreateRAMTwoBits: StructureProc = {
static: BOOL ← GetBool[context, $static];
cellType ← CreateSequenceCell[
name: IF static THEN "SRamTwoBits" ELSE "DRamTwoBits",
baseCell: CreateStructure[name: "RAMBit", context: context],
count: 2,
sequencePorts: "Word, Gnd"];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.Extract[PWCore.GetLayout[cellType]];
};
RAMBit:
ROPE = RegisterStructureProc[name: "RAMBit", proc: CreateRAMBit];
CreateRAMBit: StructureProc = {
static: BOOL ← GetBool[context, $static];
instances: InstanceList ←
LIST [
[actual: "gate: Word, ch1: Bit, ch2: State",
type: CreateTransistor[name: "Transistor", type: nE]],
[actual: "gate: Word, ch1: nBit, ch2: nState",
type: CreateTransistor[name: "Transistor", type: nE]],
[actual: "gate: nState, ch1: State, ch2: Gnd",
type: CreateTransistor[name: "Transistor", type: nE]],
[actual: "gate: State, ch1: nState, ch2: Gnd",
type: CreateTransistor[name: "Transistor", type: nE]]];
IF static
THEN {
instances ←
CONS[
[actual: "gate: State, ch1: Vdd, ch2: nState",
type: CreateTransistor[name: "Transistor", type: pE]],
instances];
instances ←
CONS[
[actual: "gate: nState, ch1: Vdd, ch2: State",
type: CreateTransistor[name: "Transistor", type: pE]],
instances];};
cellType ← CreateRecordCell[
name: IF static THEN "SRAMBit" ELSE "DRAMBit",
context: context,
public: CreateWires[context, Rope.Cat[
"Gnd, Word, Bit, nBit",
IF static THEN ", Vdd" ELSE NIL
", Vdd"
]],
onlyInternal: CreateWires[context, "State, nState"],
instances: instances];
IF GetBool[context, $Rosemary] THEN Rosemary.Bind[cellType: cellType, roseClassName: RAMBitRoseClass];
};
RAMBitRoseClass: ROPE = Rosemary.Register[roseClassName: RAMBit, init: RAMBitInit, evalSimple: RAMBitSimple];
RAMBitGnd: NAT = 0;
RAMBitWord: NAT = 1;
RAMBitBit: NAT = 2;
RAMBitnBit: NAT = 3;
RAMBitVdd: NAT = 4;
RAMBitState: TYPE = REF RAMBitStateRec;
RAMBitStateRec:
TYPE =
RECORD [
bit: BOOL ← FALSE,
nbit: BOOL ← TRUE,
static: BOOL];
RAMBitInit: Rosemary.InitProc = {
FOR port:
NAT
IN [0..p.size)
DO
p[port].type ← b;
ENDLOOP;
stateAny ← NEW[RAMBitStateRec ← [static: p.size>4]];
};
RAMBitSimple: Rosemary.EvalProc = {
state: RAMBitState ← NARROW[stateAny];
IF p[RAMBitGnd].b OR (state.static AND NOT p[RAMBitVdd].b) THEN SIGNAL Rosemary.Stop[];
IF
NOT p[RAMBitWord].b
THEN {
p[RAMBitBit].d ← none;
p[RAMBitnBit].d ← none;
}
ELSE {
state.bit ← IF state.nbit THEN FALSE ELSE p[RAMBitBit].b;
state.nbit ← IF state.bit THEN FALSE ELSE p[RAMBitnBit].b;
state.bit ← IF state.nbit THEN FALSE ELSE p[RAMBitBit].b;
p[RAMBitBit].d ← IF state.nbit THEN drive ELSE IF state.static THEN driveWeak ELSE none;
p[RAMBitBit].b ← state.bit;
p[RAMBitnBit].d ← IF state.bit THEN drive ELSE IF state.static THEN driveWeak ELSE none;
p[RAMBitnBit].b ← state.nbit;
};
};
Ports: Gnd, Word[0..2), IF static THEN Vdd
RamStitch:
ROPE = RegisterStructureProc[name: "RamStitch", proc: CreateRAMStitch];
CreateRAMStitch: StructureProc = {
static: BOOL ← GetBool[context, $static];
cellType ← CreateRecordCell[
name: IF static THEN "SRamStitch" ELSE "DRamStitch",
context: context,
public: CreateWires[context, Rope.Cat["Gnd, Word[seq: 2]",
IF static THEN ", Vdd" ELSE NIL
", Vdd"
]]];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.Extract[PWCore.GetLayout[cellType]];
};
RegisterBoolProperty[prop: $static];
END.