DIRECTORY BitOps, CD, Core, CoreClasses, CoreCreate, CoreCompose, CoreOps, IO, PW, PWCore, Rope; CrossRAMTopImpl: CEDAR PROGRAM IMPORTS BitOps, CoreCompose, CoreOps, IO, PW, PWCore, Rope EXPORTS = BEGIN OPEN CoreCompose; CrossRAMTop: ROPE = RegisterStructureProc[name: "CrossRAMTop", proc: CreateTop]; CreateTop: StructureProc = { addressBits: INT _ GetInt[context, $addressBits]; addressDecoderBits: INT _ GetInt[context, $addressDecoderBits]; columnOcts: INT _ GetInt[context, $columnOcts]; select: INT _ GetInt[context, $select]; log2Select: INT _ GetInt[context, $log2Select]; PushInt[context, $driverPairCount, (addressBits-log2Select)/2]; cellType _ CreateRecordCell[ name: CrossRAMTop, context: context, public: CreateWires[context, "Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, AddressB[seq: addressBits], DataB[seq: columnOcts], AdrBit[seq: addressDecoderBits], nAdrBit[seq: addressDecoderBits], Bit[seq: select*columnOcts], nBit[seq: select*columnOcts]"], onlyInternal: CreateWires[context, "Select[seq: select]"], instances: LIST [ [type: CreateStructure[name: "DecoderDriverLeft", context: context], -- ok actual: "AddressB: AddressB[start: 0, len: log2Select], nAdrBit: nAdrBit[start: 0, len: andDecoderBits], ch2: Vdd"], [type: CreateStructure[name: "DecoderDriverSequence", context: context], actual: "LowAddressB: AddressB[start: 0, len: log2Select], HighAddressB: AddressB[start: log2Select, len: addressBits-log2Select]"], [type: CreateStructure[name: "DecoderLogicDriver", context: context], actual: "AddressB: AddressB[start: 0, len: log2Select], AdrBit: AdrBit[addressDecoderBits-1], nAdrBit: nAdrBit[addressDecoderBits-1]"], [type: CreateStructure[name: "DataBuffer", context: context]], -- from another module [type: CreateStructure[name: "DataBufferRight", context: context]] ] ]; PWCore.SetAbutX[cellType: cellType]; }; DecoderDriverLeft: ROPE = RegisterStructureProc[name: "DecoderDriverLeft", proc: CreateDecoderDriverLeft]; CreateDecoderDriverLeft: StructureProc = { cellType _ CreateRecordCell[ name: DecoderDriverLeft, context: context, public: CreateWires[context, "Vdd, AddressB[seq: log2Select]"]]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; DecoderDriverSequence: ROPE = RegisterStructureProc[name: "DecoderDriverSequence", proc: CreateDecoderDriverSequence]; CreateDecoderDriverSequence: StructureProc = { driverCount: INT _ 2*GetInt[context, $driverPairCount]; MakeStackRope: PROC [base: ROPE] RETURNS [ROPE] = { RETURN[IO.PutFR["%g: %g[start:0, len:%g]", IO.rope[base], IO.rope[base], IO.int[driverCount-2]]];}; MakePairRope: PROC [base: ROPE] RETURNS [ROPE] = { RETURN[IO.PutFR["%g: %g[start:%g, len:2]", IO.rope[base], IO.rope[base], IO.int[driverCount-2]]];}; cellType _ CreateRecordCell[ name: DecoderDriverSequence, context: context, public: CreateWires[context, "Vdd, Gnd, LowAddressB[seq: log2Select], HighAddressB[seq: 2*driverPairCount], AdrBit[seq: 2*driverPairCount], nAdrBit[seq: 2*driverPairCount]"], instances: LIST [ [type: CreateStructure[name: "DecoderDriverStackBitSeq", context: context], actual: Rope.Cat[MakeStackRope["HighAddressB"], ", ", MakeStackRope["AdrBit"], ", ", MakeStackRope["nAdrBit"]]], [type: CreateStructure[name: "DecoderDriverTreeBit", context: context], actual: Rope.Cat[MakePairRope["HighAddressB"], ", ", MakePairRope["AdrBit"], ", ", MakePairRope["nAdrBit"]]] ] ]; PWCore.SetAbutX[cellType: cellType]; }; DecoderDriverStackBitSeq: ROPE = RegisterStructureProc[name: "DecoderDriverStackBitSeq", proc: CreateDecoderDriverStackBitSeq]; CreateDecoderDriverStackBitSeq: StructureProc = { cellType _ CreateSequenceCell[ name: DecoderDriverStackBitSeq, baseCell: CreateStructure[name: "DecoderDriverStackBit", context: context], count: GetInt[context: context, prop: $driverPairCount]-1, sequencePorts: "HighAddressB, AdrBit, nAdrBit"]; PWCore.SetArrayX[cellType: cellType]; }; DecoderDriverStackBit: ROPE = RegisterStructureProc[name: "DecoderDriverStackBit", proc: CreateDecoderDriverStackBit]; CreateDecoderDriverStackBit: StructureProc = { decoderDriver: Core.CellType _ CreateStructure[name: "DecoderDriver", context: context]; cellType _ CreateRecordCell[ name: DecoderDriverStackBit, context: context, public: CoreOps.CopyWire[decoderDriver.public], instances: LIST [[type: decoderDriver]]]; -- true??? PWCore.SetLayout[cellType, PW.Inst[NIL, PWCore.GetLayout[decoderDriver], LIST["RemoveForStackDecoderBit"]]]; }; DecoderDriverTreeBit: ROPE = RegisterStructureProc[name: "DecoderDriverTreeBit", proc: CreateDecoderDriverTreeBit]; CreateDecoderDriverTreeBit: StructureProc = { decoderDriver: Core.CellType _ CreateStructure[name: "DecoderDriver", context: context]; cellType _ CreateRecordCell[ name: DecoderDriverTreeBit, context: context, public: CoreOps.CopyWire[decoderDriver.public], instances: LIST [[type: decoderDriver]]]; -- true??? PWCore.SetLayout[cellType, PW.Inst[NIL, PWCore.GetLayout[decoderDriver], LIST["RemoveForTreeDecoderBit"]]]; }; DecoderDriver: ROPE = RegisterStructureProc[name: "DecoderDriver", proc: CreateDecoderDriver]; CreateDecoderDriver: StructureProc = { cellType _ CreateSequenceCell[ name: DecoderDriver, baseCell: CreateStructure[name: "DecoderDriverHalf", context: context], count: 2, sequencePorts: "HighAddressB, AdrBit, nAdrBit"]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; DecoderDriverHalf: ROPE = RegisterStructureProc[name: "DecoderDriverHalf", proc: CreateDecoderDriverHalf]; CreateDecoderDriverHalf: StructureProc = { cellType _ CreateRecordCell[ name: DecoderDriverHalf, context: context, public: CreateWires[context, "Vdd, Gnd, HighAddressB, AdrBit, nAdrBit, LowAddressB[seq: log2Select]"], onlyInternal: CreateWires[context, "nAddress"], instances: LIST [ [actual: "Input: HighAddressB, Output: nAddress", type: CreateStructure[name: "Inverter", context: context]], -- width: 4 [actual: "Input: nAddress, Output: AdrBit", type: CreateStructure[name: "Inverter", context: context]], -- width: 16 [actual: "Input: HighAddressB, Output: nAdrBit", type: CreateStructure[name: "Inverter", context: context]]]]; -- width: 16 }; DecoderLogicDriver: ROPE = RegisterStructureProc[name: "DecoderLogicDriver", proc: CreateDecoderLogicDriver]; CreateDecoderLogicDriver: StructureProc = { select: INT _ 2*GetInt[context, $select]; log2Select: INT _ 2*GetInt[context, $log2Select]; invert8: Core.CellType _ CreateStructure[name: "Inverter", context: context]; -- width: 8 and: Core.CellType _ CreateStructure[name: "And", context: context]; -- inputCount: log2Select, width: 16 instances: InstanceList _ NIL; -- fill in! FOR adrBit: INT IN [0..log2Select) DO instances _ CONS[[type: invert8, actual: IO.PutFR["Input: AddressB[%g], Output: nHighAddressB[%g]", IO.int[adrBit], IO.int[adrBit]]], instances]; ENDLOOP; FOR sel: INT IN [0..select) DO bind: ROPE _ NIL; FOR adrBit: INT IN [0..log2Select) DO bind _ Rope.Cat[bind, IF BitOps.EBFW[sel, log2Select, adrBit] THEN IO.PutFR["AddressB[%g]", IO.int[adrBit]] ELSE IO.PutFR["nHighAddressB[%g]", IO.int[adrBit]]]; IF adrBit < log2Select-1 THEN bind _ Rope.Cat[bind, ", "]; ENDLOOP; instances _ CONS[ [type: CreateStructure[name: "And", context: context], actual: IO.PutFR["Input: [%g], Output: Select[%g]", IO.rope[bind], IO.int[sel]]], instances]; ENDLOOP; cellType _ CreateRecordCell[ name: DecoderLogicDriver, context: context, public: CreateWires[context, "Vdd, Gnd, AdrBit, nAdrBit, AddressB[seq: log2Select], Select[seq: select]"], onlyInternal: CreateWires[context, "nHighAddressB[seq: log2Select]"], instances: instances]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; DataBufferRight: ROPE = RegisterStructureProc[name: "DataBufferRight", proc: CreateDataBufferRight]; CreateDataBufferRight: StructureProc = { cellType _ CreateRecordCell[ name: DataBufferRight, context: context, public: CreateWires[context, "Vdd, WriteB, nWriteB, ReadB, nReadB"]]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; END. pCrossRAMTopImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Barth, September 26, 1985 2:17:26 pm PDT Louis Monier October 25, 1985 12:09:38 pm PDT addressBits, addressDecoderBits, columnOcts, select, log2Select: NAT Ports: Vdd, AddressB[0..log2Select) Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB[0..2*driverPairCount), AdrBit[0..2*driverPairCount), nAdrBit[0..2*driverPairCount) -- ArrayX of PW.Inst[decoderDriver, "RemoveForStackDecoderBit"] -- PW.Inst[decoderDriver, "RemoveForTreeDecoderBit"] Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB[0..2), AdrBit[0..2), nAdrBit[0..2), Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB, AdrBit, nAdrBit Ports: Vdd, Gnd, AddressB[0..log2Select), AdrBit, nAdrBit, Select[0..select) -- Drop three inverters -- Drop eight nand gates Ports: Vdd, WriteB, nWriteB, ReadB, nReadB Êõ– "cedar" style˜codešœ™Kšœ Ïmœ1™