DIRECTORY CoreCompose, IO, PWCore, Rope; CrossRAMRAMImpl: CEDAR PROGRAM IMPORTS CoreCompose, IO, PWCore, Rope EXPORTS = BEGIN OPEN CoreCompose; RAMArray: ROPE = RegisterStructureProc[name: "RAMArray", proc: CreateRAM]; CreateRAM: StructureProc = { static, dynamic: InstanceRec; PushBool[context, $static, TRUE]; static _ [actual: "Word: Word[0, 2*rowQuads]", type: CreateStructure[name: "RAMArray", context: context]]; PushBool[context, $static, FALSE]; dynamic _ [actual: "Word: Word[2*rowQuads, 2*rowQuads]", type: CreateStructure[name: "RAMArray", context: context]]; cellType _ CreateRecordCell[ name: RAMArray, context: context, public: CreateWires[context, "Vdd, Gnd, Word[SEQ:4*rowQuads], Bit[SEQ:8*columnOcts], nBit[SEQ:8*columnOcts]"], instances: LIST [static, dynamic]]; PWCore.SetAbutY[cellType: cellType]; }; SubArray: ROPE = RegisterStructureProc[name: "SubArray", proc: CreateSubArray]; CreateSubArray: StructureProc = { static: BOOL _ GetBool[context, $static]; rowQuads: INT _ GetInt[context, $rowQuads]; cellType _ CreateSequenceCell[ name: IF static THEN "SSubArray" ELSE "DSubArray", baseCell: CreateStructure[name: RamRow, context: context], count: rowQuads, sequencePorts: "Word"]; PWCore.SetArrayY[cellType: cellType]; }; RamRow: ROPE = RegisterStructureProc[name: "RamRow", proc: CreateRAMRow]; CreateRAMRow: StructureProc = { static: BOOL _ GetBool[context, $static]; columnOcts: INT _ GetInt[context, $columnOcts]; cellType _ CreateSequenceCell[ name: IO.PutFR["%g*%g", IF static THEN IO.rope["SRamRow"] ELSE IO.rope["DRamRow"], IO.int[columnOcts]], baseCell: CreateStructure[name: RamOctStitch, context: context], count: columnOcts, sequencePorts: "Bit, nBit"]; PWCore.SetArrayX[cellType: cellType]; }; RamOctStitch: ROPE = RegisterStructureProc[name: "RamOctStitch", proc: CreateRAMOctStitch]; CreateRAMOctStitch: StructureProc = { static: BOOL _ GetBool[context, $static]; cellType _ CreateRecordCell[ name: IF static THEN "SRamOctStitch" ELSE "DRamOctStitch", context: context, public: CreateWires[context, "Gnd, Word[SEQ:2], Bit[SEQ:8], nBit[SEQ:8]"], instances: LIST [ [type: CreateStructure[name: "RamOct", context: context]], [type: CreateStructure[name: "RamStitch", context: context]]]]; PWCore.SetAbutX[cellType: cellType]; }; RamOct: ROPE = RegisterStructureProc[name: "RamOct", proc: CreateRAMOct]; CreateRAMOct: StructureProc = { static: BOOL _ GetBool[context, $static]; cellType _ CreateSequenceCell[ name: IF static THEN "SRamOct" ELSE "DRamOct", baseCell: CreateStructure[name: "RamTwoBits", context: context], count: 8, sequencePorts: "Bit, nBit"]; PWCore.SetArrayX[cellType: cellType]; }; RamTwoBits: ROPE = RegisterStructureProc[name: "RamTwoBits", proc: CreateTwoRAMBits]; CreateTwoRAMBits: StructureProc = { static: BOOL _ GetBool[context, $static]; cellType _ CreateSequenceCell[ name: IF static THEN "SRamTwoBits" ELSE "DRamTwoBits", baseCell: CreateStructure[name: "RAMBit", context: context], count: 2, sequencePorts: "Word"]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; RAMBit: ROPE = RegisterStructureProc[name: "RAMBit", proc: CreateRAMBit]; CreateRAMBit: StructureProc = { static: BOOL _ GetBool[context, $static]; instances: InstanceList _ LIST [ [actual: "gate: Word, ch1: Bit, ch2: State", type: CreateTransistor[name: "Transistor", type: nE]], [actual: "gate: Word, ch1: nBit, ch2: nState", type: CreateTransistor[name: "Transistor", type: nE]], [actual: "gate: nState, ch1: State, ch2: Gnd", type: CreateTransistor[name: "Transistor", type: nE]], [actual: "gate: State, ch1: nState, ch2: Gnd", type: CreateTransistor[name: "Transistor", type: nE]]]; IF static THEN { instances _ CONS[ [actual: "gate: State, ch1: Vdd, ch2: nState", type: CreateTransistor[name: "Transistor", type: pE]], instances]; instances _ CONS[ [actual: "gate: nState, ch1: Vdd, ch2: State", type: CreateTransistor[name: "Transistor", type: pE]], instances];}; cellType _ CreateRecordCell[ name: IF static THEN "SRAMBit" ELSE "DRAMBit", context: context, public: CreateWires[context, Rope.Cat[ "Gnd, Word, Bit, nBit", IF static THEN ", Vdd" ELSE NIL]], onlyInternal: CreateWires[context, "State, nState"], instances: instances]; }; RamStitch: ROPE = RegisterStructureProc[name: "RamStitch", proc: CreateRAMStitch]; CreateRAMStitch: StructureProc = { static: BOOL _ GetBool[context, $static]; cellType _ CreateRecordCell[ name: IF static THEN "SRamStitch" ELSE "DRamStitch", context: context, public: CreateWires[context, Rope.Cat["Gnd, Word[SEQ:2]", IF static THEN ", Vdd" ELSE NIL]]]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; END. bCrossRAMRAMImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Barth, September 26, 1985 1:56:35 pm PDT Louis Monier October 23, 1985 6:35:23 pm PDT columnOcts, rowQuads: INT, static: BOOL columnOcts, rowQuads: INT Ports: Gnd, Word[0..2), Bit[0..8*columnOcts), nBit[0..8*columnOcts), IF static THEN Vdd Ports: Gnd, Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd Ports: Gnd, Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd Ports: Gnd, Word[0..2), Bit, nBit, IF static THEN Vdd Ports: Gnd, Word, Bit, nBit, IF static THEN Vdd Ports: Gnd, Word[0..2), IF static THEN Vdd Êo– "cedar" style˜codešœ™Kšœ Ïmœ1™