<> <> <<>> DIRECTORY Core, CoreClasses; Rosemary: CEDAR DEFINITIONS = BEGIN ROPE : TYPE = Core.ROPE; ValueWireList: TYPE = LIST OF ValueWire; ValueWire: TYPE = REF ValueWireRec; ValueWireRec: TYPE = RECORD [ <> nextStrengthRingMember: ValueWire _ NIL, previousStrengthRingMember: ValueWire _ NIL, currentRing: Drive _ none, internal: InternalValueWire _ NIL, fieldSize: CARDINAL _ 0, coreWire: Core.Wire _ NIL, roseCellInstance: RoseCellInstance _ NIL, d: Drive _ none, type: ValueWireType _ none, -- IF Core.Wire = atom THEN l ELSE none, l: Level _ L, b: BOOL _ FALSE, c: CARDINAL _ 0, lc: LONG CARDINAL _ 0, sub: SEQUENCE size: NAT OF ValueWire]; Drive: TYPE = { expect, -- allows test procs to put expected value in none, --from a test proc it means neither driven nor checked; in switch-level it means no strength at all force, -- weakest drive level, allows test procs to check if device has tristated chargeWeak, chargeMediumWeak, charge, chargeMediumStrong, chargeStrong, chargeVeryStrong, driveWeak, driveMediumWeak, drive, driveMediumStrong, driveStrong, driveVeryStrong, input -- the strongest drive level }; ValueWireType: TYPE = {none, l, b, c, lc, sub}; Level: TYPE = {L, H, X}; <> Bind: PROC [cellType: Core.CellType, roseClassName: Core.ROPE]; Register: PROC [roseClassName: Core.ROPE, init: InitProc _ NIL, evalSimple: EvalProc _ NIL] RETURNS [sameRoseClassName: Core.ROPE]; InitProc: TYPE = PROC [cellType: Core.CellType, p: ValueWire] RETURNS [stateAny: REF ANY _ NIL]; <> <<>> EvalProc: TYPE = PROC [p: ValueWire, stateAny: REF ANY]; Stop: SIGNAL [msg: ROPE _ NIL, data: REF ANY _ NIL]; <> <> Simulation: TYPE = REF SimulationRec; InstantiateCellType: PROC [cellType: Core.CellType] RETURNS [simulation: Simulation]; <> InstantiateInstances: PROC [cellType: Core.CellType] RETURNS [simulation: Simulation]; <> Initialize: PROC [simulation: Simulation, steady: BOOL _ TRUE]; <> <<>> Settle: PROC [simulation: Simulation]; <> <<>> GetValue: PROC [wire: Core.Wire] RETURNS [value: ValueWire]; <> <<>> RefreshValue: PROC [value: ValueWire]; <> <<>> SetValue: PROC [simulation: Simulation, value: ValueWire]; <> <<>> PrintValue: PROC [value: ValueWire, out: Core.STREAM]; <> <<>> PrintDrivers: PROC [value: ValueWire, out: Core.STREAM]; <> <<>> PrintWriters: PROC [value: ValueWire, out: Core.STREAM]; <> <<>> <> RegisterTest: PROC [testName: ROPE, testProc: CellTestProc]; CellTestProc: TYPE = PROC [p: ValueWire, Eval: PROC]; RunTest: PROC [simulation: Simulation, testName: ROPE]; <<>> <> SimulationRec: TYPE = RECORD [ cellType: Core.CellType, roseCellInstances: RoseCellInstances _ NIL, needEval: RoseCellInstance _ NIL, internal: InternalValueWires _ NIL, publicValue: ValueWire _ NIL]; RoseCellType: TYPE = REF RoseCellTypeRec; RoseCellTypeRec: TYPE = RECORD [ init: InitProc _ NIL, evalSimple: EvalProc _ NIL]; RoseCellInstances: TYPE = LIST OF RoseCellInstance; RoseCellInstance: TYPE = REF RoseCellInstanceRec; RoseCellInstanceRec: TYPE = RECORD [ scheduleNext: RoseCellInstance _ NIL, roseCellType: RoseCellType, coreCellInstance: CoreClasses.CellInstance, value: ValueWire, state: REF ANY _ NIL]; InternalValueWires: TYPE = LIST OF InternalValueWire; InternalValueWire: TYPE = REF InternalValueWireRec; InternalValueWireRec: TYPE = RECORD [ l: Level _ L, writers: RoseCellInstances _ NIL, writerValues: ARRAY Drive OF ValueWire _ ALL[NIL], readers: RoseCellInstances _ NIL, readerValues: ValueWireList _ NIL]; END.