CrossRAMTopImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 26, 1985 2:17:26 pm PDT
Louis Monier October 25, 1985 12:09:38 pm PDT
DIRECTORY BitOps, CD, Core, CoreClasses, CoreCreate, CoreCompose, CoreOps, IO, PW, PWCore, Rope;
CrossRAMTopImpl:
CEDAR
PROGRAM
IMPORTS BitOps, CoreCompose, CoreOps, IO, PW, PWCore, Rope
EXPORTS =
BEGIN OPEN CoreCompose;
addressBits, addressDecoderBits, columnOcts, select, log2Select: NAT
CrossRAMTop: ROPE = RegisterStructureProc[name: "CrossRAMTop", proc: CreateTop];
CreateTop: StructureProc = {
addressBits: INT ← GetInt[context, $addressBits];
addressDecoderBits: INT ← GetInt[context, $addressDecoderBits];
columnOcts: INT ← GetInt[context, $columnOcts];
select: INT ← GetInt[context, $select];
log2Select: INT ← GetInt[context, $log2Select];
PushInt[context, $driverPairCount, (addressBits-log2Select)/2];
cellType ← CreateRecordCell[
name: CrossRAMTop,
context: context,
public: CreateWires[context, "Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB,
AddressB[seq: addressBits],
DataB[seq: columnOcts],
AdrBit[seq: addressDecoderBits], nAdrBit[seq: addressDecoderBits],
Bit[seq: select*columnOcts], nBit[seq: select*columnOcts]"],
onlyInternal: CreateWires[context, "Select[seq: select]"],
instances:
LIST [
[type: CreateStructure[name: "DecoderDriverLeft", context: context],
-- ok
actual: "AddressB: AddressB[start: 0, len: log2Select],
nAdrBit: nAdrBit[start: 0, len: andDecoderBits], ch2: Vdd"],
[type: CreateStructure[name: "DecoderDriverSequence", context: context],
actual: "LowAddressB: AddressB[start: 0, len: log2Select],
HighAddressB: AddressB[start: log2Select, len: addressBits-log2Select]"],
[type: CreateStructure[name: "DecoderLogicDriver", context: context],
actual: "AddressB: AddressB[start: 0, len: log2Select],
AdrBit: AdrBit[addressDecoderBits-1],
nAdrBit: nAdrBit[addressDecoderBits-1]"],
[type: CreateStructure[name: "DataBuffer", context: context]], -- from another module
[type: CreateStructure[name: "DataBufferRight", context: context]]
]
];
PWCore.SetAbutX[cellType: cellType];
};
Ports: Vdd, AddressB[0..log2Select)
DecoderDriverLeft: ROPE = RegisterStructureProc[name: "DecoderDriverLeft", proc: CreateDecoderDriverLeft];
CreateDecoderDriverLeft: StructureProc = {
cellType ← CreateRecordCell[
name: DecoderDriverLeft,
context: context,
public: CreateWires[context, "Vdd, AddressB[seq: log2Select]"]];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB[0..2*driverPairCount), AdrBit[0..2*driverPairCount), nAdrBit[0..2*driverPairCount)
DecoderDriverSequence: ROPE = RegisterStructureProc[name: "DecoderDriverSequence", proc: CreateDecoderDriverSequence];
CreateDecoderDriverSequence: StructureProc = {
driverCount: INT ← 2*GetInt[context, $driverPairCount];
MakeStackRope:
PROC [base:
ROPE]
RETURNS [
ROPE] = {
RETURN[IO.PutFR["%g: %g[start:0, len:%g]", IO.rope[base], IO.rope[base], IO.int[driverCount-2]]];};
MakePairRope:
PROC [base:
ROPE]
RETURNS [
ROPE] = {
RETURN[IO.PutFR["%g: %g[start:%g, len:2]", IO.rope[base], IO.rope[base], IO.int[driverCount-2]]];};
cellType ← CreateRecordCell[
name: DecoderDriverSequence,
context: context,
public: CreateWires[context,
"Vdd, Gnd,
LowAddressB[seq: log2Select],
HighAddressB[seq: 2*driverPairCount],
AdrBit[seq: 2*driverPairCount], nAdrBit[seq: 2*driverPairCount]"],
instances:
LIST [
[type: CreateStructure[name: "DecoderDriverStackBitSeq", context: context],
actual: Rope.Cat[MakeStackRope["HighAddressB"], ", ", MakeStackRope["AdrBit"], ", ", MakeStackRope["nAdrBit"]]],
[type: CreateStructure[name: "DecoderDriverTreeBit", context: context],
actual: Rope.Cat[MakePairRope["HighAddressB"], ", ", MakePairRope["AdrBit"], ", ", MakePairRope["nAdrBit"]]]
]
];
PWCore.SetAbutX[cellType: cellType];
};
-- ArrayX of PW.Inst[decoderDriver, "RemoveForStackDecoderBit"]
DecoderDriverStackBitSeq: ROPE = RegisterStructureProc[name: "DecoderDriverStackBitSeq", proc: CreateDecoderDriverStackBitSeq];
CreateDecoderDriverStackBitSeq: StructureProc = {
cellType ← CreateSequenceCell[
name: DecoderDriverStackBitSeq,
baseCell: CreateStructure[name: "DecoderDriverStackBit", context: context],
count: GetInt[context: context, prop: $driverPairCount]-1,
sequencePorts: "HighAddressB, AdrBit, nAdrBit"];
PWCore.SetArrayX[cellType: cellType];
};
DecoderDriverStackBit: ROPE = RegisterStructureProc[name: "DecoderDriverStackBit", proc: CreateDecoderDriverStackBit];
CreateDecoderDriverStackBit: StructureProc = {
decoderDriver: Core.CellType ← CreateStructure[name: "DecoderDriver", context: context];
cellType ← CreateRecordCell[
name: DecoderDriverStackBit,
context: context,
public: CoreOps.CopyWire[decoderDriver.public],
instances: LIST [[type: decoderDriver]]]; -- true???
PWCore.SetLayout[cellType, PW.Inst[NIL, PWCore.GetLayout[decoderDriver], LIST["RemoveForStackDecoderBit"]]];
};
-- PW.Inst[decoderDriver, "RemoveForTreeDecoderBit"]
DecoderDriverTreeBit: ROPE = RegisterStructureProc[name: "DecoderDriverTreeBit", proc: CreateDecoderDriverTreeBit];
CreateDecoderDriverTreeBit: StructureProc = {
decoderDriver: Core.CellType ← CreateStructure[name: "DecoderDriver", context: context];
cellType ← CreateRecordCell[
name: DecoderDriverTreeBit,
context: context,
public: CoreOps.CopyWire[decoderDriver.public],
instances: LIST [[type: decoderDriver]]]; -- true???
PWCore.SetLayout[cellType, PW.Inst[NIL, PWCore.GetLayout[decoderDriver], LIST["RemoveForTreeDecoderBit"]]];
};
Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB[0..2), AdrBit[0..2), nAdrBit[0..2),
DecoderDriver: ROPE = RegisterStructureProc[name: "DecoderDriver", proc: CreateDecoderDriver];
CreateDecoderDriver: StructureProc = {
cellType ← CreateSequenceCell[
name: DecoderDriver,
baseCell: CreateStructure[name: "DecoderDriverHalf", context: context],
count: 2,
sequencePorts: "HighAddressB, AdrBit, nAdrBit"];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB, AdrBit, nAdrBit
DecoderDriverHalf: ROPE = RegisterStructureProc[name: "DecoderDriverHalf", proc: CreateDecoderDriverHalf];
CreateDecoderDriverHalf: StructureProc = {
cellType ← CreateRecordCell[
name: DecoderDriverHalf,
context: context,
public: CreateWires[context, "Vdd, Gnd, HighAddressB, AdrBit, nAdrBit, LowAddressB[seq: log2Select]"],
onlyInternal: CreateWires[context, "nAddress"],
instances:
LIST [
[actual: "Input: HighAddressB, Output: nAddress",
type: CreateStructure[name: "Inverter", context: context]], -- width: 4
[actual: "Input: nAddress, Output: AdrBit",
type: CreateStructure[name: "Inverter", context: context]], -- width: 16
[actual: "Input: HighAddressB, Output: nAdrBit",
type: CreateStructure[name: "Inverter", context: context]]]]; -- width: 16
};
Ports: Vdd, Gnd, AddressB[0..log2Select), AdrBit, nAdrBit, Select[0..select)
DecoderLogicDriver: ROPE = RegisterStructureProc[name: "DecoderLogicDriver", proc: CreateDecoderLogicDriver];
CreateDecoderLogicDriver: StructureProc = {
select: INT ← 2*GetInt[context, $select];
log2Select: INT ← 2*GetInt[context, $log2Select];
invert8: Core.CellType ← CreateStructure[name: "Inverter", context: context]; -- width: 8
and: Core.CellType ← CreateStructure[name: "And", context: context]; -- inputCount: log2Select, width: 16
instances: InstanceList ← NIL; -- fill in!
-- Drop three inverters
FOR adrBit:
INT
IN [0..log2Select)
DO
instances ← CONS[[type: invert8, actual: IO.PutFR["Input: AddressB[%g], Output: nHighAddressB[%g]", IO.int[adrBit], IO.int[adrBit]]], instances];
ENDLOOP;
-- Drop eight nand gates
FOR sel:
INT
IN [0..select)
DO
bind: ROPE ← NIL;
FOR adrBit:
INT
IN [0..log2Select)
DO
bind ← Rope.Cat[bind, IF BitOps.EBFW[sel, log2Select, adrBit] THEN IO.PutFR["AddressB[%g]", IO.int[adrBit]] ELSE IO.PutFR["nHighAddressB[%g]", IO.int[adrBit]]];
IF adrBit < log2Select-1 THEN bind ← Rope.Cat[bind, ", "];
ENDLOOP;
instances ←
CONS[
[type: CreateStructure[name: "And", context: context],
actual: IO.PutFR["Input: [%g], Output: Select[%g]", IO.rope[bind], IO.int[sel]]],
instances];
ENDLOOP;
cellType ← CreateRecordCell[
name: DecoderLogicDriver,
context: context,
public: CreateWires[context, "Vdd, Gnd, AdrBit, nAdrBit, AddressB[seq: log2Select], Select[seq: select]"],
onlyInternal: CreateWires[context, "nHighAddressB[seq: log2Select]"],
instances: instances];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Vdd, WriteB, nWriteB, ReadB, nReadB
DataBufferRight: ROPE = RegisterStructureProc[name: "DataBufferRight", proc: CreateDataBufferRight];
CreateDataBufferRight: StructureProc = {
cellType ← CreateRecordCell[
name: DataBufferRight,
context: context,
public: CreateWires[context, "Vdd, WriteB, nWriteB, ReadB, nReadB"]];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
END.