Write2Read2: Rosemary.CellTestProc = {
AccessRAM:
PROC [write:
BOOL, address:
CARDINAL, data:
CARDINAL] = {
p[Address].c ← address;
precharge
p[nPrecharge].b ← FALSE;
Eval[];
p[nPrecharge].b ← TRUE;
Eval[];
enable select line
p[Access].b ← TRUE;
if write then enable write drivers
IF write
THEN {
p[Data].d ← force;
p[Write].b ← TRUE;
}
ELSE {
p[Data].d ← expect;
p[Read].b ← TRUE;
};
p[Data].c ← data;
Eval[];
disable select line
p[Access].b ← p[Write].b ← p[Read].b ← FALSE;
p[Data].d ← none;
Eval[];
};
p[Vdd].b ← TRUE; p[Gnd].b ← FALSE;
p[Vdd].d ← force; p[Gnd].d ← force;
p[Vdd].type ← b; p[Gnd].type ← b;
p[PadVdd].b ← TRUE; p[PadGnd].b ← FALSE;
p[PadVdd].d ← force; p[PadGnd].d ← force;
p[PadVdd].type ← b; p[PadGnd].type ← b;
p[nPrecharge].b ← TRUE; p[Access].b ← FALSE;
p[nPrecharge].d ← force; p[Access].d ← force;
p[nPrecharge].type ← b; p[Access].type ← b;
p[Write].b ← FALSE; p[Read].b ← FALSE;
p[Write].d ← force; p[Read].d ← force;
p[Write].type ← b; p[Read].type ← b;
p[Address].d ← force;
p[Address].type ← c;
FOR port:
NAT
IN [0..p[Address].size)
DO
p[Address][port].type ← sub;
ENDLOOP;
p[Data].d ← none;
p[Data].type ← c;
FOR port:
NAT
IN [0..p[Data].size)
DO
p[Data][port].type ← sub;
ENDLOOP;
Eval[! Rosemary.Stop => RESUME];
AccessRAM[write: TRUE, address: 0, data: 0];
AccessRAM[write: TRUE, address: 1, data: LAST[CARDINAL]];
AccessRAM[write: FALSE, address: 0, data: 0];
AccessRAM[write: FALSE, address: 1, data: LAST[CARDINAL]];
};